BLUENRG-2 datasheet(25/190 Pages) STMICROELECTRONICS

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BlueNRG-2

Functional details

DocID030675 Rev 2

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Figure 9: Reset circuit

If the above conditions are not satisfied, ST cannot guarantee the correct operation of the

device.

3.5.1.3

Watchdog reset

The BlueNRG-2 contains a watchdog timer, which may be used to recover from software

crashes. The watchdog contains a 32-bit down counter, which generates an interrupt, if the

interrupt is not serviced, the watchdog will generate a reset. The watchdog Reset resets

the Flash controller, the Cortex-M0 and all its peripherals but it does not reset the debug

circuitry of the Cortex-M0.

3.5.1.4

System reset request

The system reset request is generated by the debug circuitry of the Cortex-M0. The

debugger writes

to the SYSRESETREQ bit of the “Application Interrupt and Reset Control

embedded software. The system reset request does not affect the debugger, thus allowing

the debugger to remain connected during the reset sequence.

3.5.1.5

Lockup reset

The Cortex-M0 generates an output LOCKUP that indicates that the core is in a deliberate

lock-up state resulting from an unrecoverable exception. The LOCKUP signal is used to

generate a reset in the BlueNRG-2, which affects the Cortex-M0, the Flash controller and

all the peripherals.

The LOCKUP signal does not reset the Cortex-M0 debug circuitry and it is not generated if

a debugger is connected.

3.5.2

Reset and wakeup reason decoding

The BlueNRG-2 provides a set of registers to identify the reason behind a reset and

wakeup generation. Two registers are used: CKGEN_SOC->REASON_RST and

CKGEN_BLE->REASON_RST. The possible reasons are listed below:

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