BLUENRG-2 datasheet(90/190 Pages) STMICROELECTRONICS

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Functional details

BlueNRG-2

90/190

DocID030675 Rev 2

3.10.2

Functional description

Two wires, serial data (SDA) and serial clock (SCL) carry information between the devices

connected to the bus. Each device has a unique address and can operate as either a

transmitter or receiver, depending on the function of the device. A master is the device that

initiates a data transfer on the bus and generates the clock signal. Any device addressed is

considered at that time a slave. The I²C bus is a multi-master bus where more than one

device is capable of controlling the bus. This means that more than one master could try to

initiate a data transfer at the same time. The arbitration procedure relies on the wired-AND

connection of all I²C interfaces to the I²C bus. If two or more masters try to put information

onto the bus, the first to produce a ‘one’ when the other produces a ‘zero’ will lose the

arbitration. The clock signals during arbitration are a synchronized combination of the

clocks generated by the masters using the wired-AND connection to the SCL line.

Generation of clock signals on the I²C bus is always the responsibility of master devices;

each master generates its own clock signals when transferring data to the bus. Bus clock

signals from a master can only be altered when they are stretched by a slow slave device

holding down the clock line, or by another master when arbitration occurs.

Two modes:



Standard mode with bit rate up to 100 Kb/s



Fast mode with bit rate up to 400 Kb/s

3.10.2.1

I²C FIFO management

The transmit and receive paths are buffered with internal FIFO memory enabling up to 16

bytes to be stored independently in both transmit and receive modes. The FIFOs status

can be checked using the I²C interrupts. There is a programmable threshold value for each

FIFO. When the number of entries is greater for the receive FIFO or less for the transmit

FIFO, an interrupt is set.

3.10.2.2

I²C clock rate calculation

To define the I²C clock rate generation there is one register to configure: BRCR. The clock

rate can be calculated using this formula:

Where:



fI2C is the I²C peripheral clock, clocked on the system clock divided by 3.



BRCNT2 is a field of the BRCR register.



Foncycle depends on a programmable field of the CR register:



CR: FON = “00” → Filter the clock spike wide = 0 → Foncycle = 1



CR: FON = “01” → Filter the clock spike wide = 1 → Foncycle = 3



CR: FON = “10” → Filter the clock spike wide = 2 → Foncycle = 4



CR: FON = “11” → Filter the clock spike wide = 4 → Foncycle = 6

The minimum input clock frequency for the I²C is:



1.4 MHz if the I²C is in standard mode at 100 kHz.



7.2 MHz if the I²C is in fast mode at 400 kHz.

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