BLUENRG-2 datasheet(49/190 Pages) STMICROELECTRONICS

49 / 190 page

BlueNRG-2

Functional details

DocID030675 Rev 2

49/190

Bit

Field name

Reset

Description

TEIF4

0x0

Channel 4 transfer error flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 4.

1: A transfer error (TE) occurred on channel 4.

GIF5

0x0

Channel 5 global interrupt flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 5.

1: A TE, HT or TC event occurred on channel 5.

TCIF5

0x0

Channel 5 transfer complete flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 5.

1: A transfer complete (TC) occurred on channel 5.

HTIF5

0x0

Channel 5 half transfer flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 5.

1: A half transfer (HT) event occurred on channel 5.

TEIF5

0x0

Channel 5 transfer error flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 5.

1: A transfer error (TE) occurred on channel 5.

GIF6

0x0

Channel 6 global interrupt flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No TE, HT or TC event on channel 6.

1: A TE, HT or TC event occurred on channel 6.

TCIF6

0x0

Channel 6 transfer complete flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No transfer complete (TC) on channel 6.

1: A transfer complete (TC) occurred on channel 6.

HTIF6

0x0

Channel 6 half transfer flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No half transfer (HT) event on channel 6.

1: A half transfer (HT) event occurred on channel 6.

TEIF6

0x0

Channel 6 transfer error flag. This bit is set by

hardware. It is cleared by software writing 1 to the

corresponding bit in the IFCR register.

0: No transfer error (TE) event on channel 6.

1: A transfer error (TE) occurred on channel 6.

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