BLUENRG-2 datasheet(23/190 Pages) STMICROELECTRONICS

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BlueNRG-2

Functional details

DocID030675 Rev 2

23/190



ADC



MFT1



MFT2



RTC



WDG



PKA

By default, all the peripheral APB and AHB clocks are enabled, except for the PKA

peripheral. The following clocks are enabled/disabled automatically:



Processor clock (disabled in sleep mode)



RAM clock (disabled if processor clock, SPI clock and BLE clock are all disabled)

3.5.1

Reset management

Figure 7: "Reset and wakeup generation" shows the general principle of reset. Releasing

the Reset pin puts the chip out of shutdown state. The wakeup logic is powered and

receives the POR. Each time the wake-up controller decides to exit sleep or standby

modes, it will generate a reset for the core logic. The core logic can also be reset by:



Watchdog



Reset request from the processor (system reset)



LOCKUP state of the Cortex-M0.

The SWD logic is reset by the POR. It is important to highlight that reset pin actually power

down chip, so it is not possible to perform debug access with system under reset.

Figure 7: Reset and wakeup generation

If, for any reason, the users would like to power off the device there are two options:

Force RESETN pin to ground, keeping VBAT level

To put VBAT pins to ground (e.g. via a transistor)

In the second option, care must be taken to ensure that no voltage is applied to any of the

other pins since device can be powered and having an anomalous power consumption. ST

recommendation is to use RESETN whenever it is possible.

3.5.1.1

Power-on-Reset

The Power-on-Reset (POR) signal is the combination of the POR signal and the BOR

signal generated by the analog circuitry contained in the BlueNRG-2 device. The

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