BLUENRG-2 datasheet(102/190 Pages) STMICROELECTRONICS

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Functional details

BlueNRG-2

102/190

DocID030675 Rev 2

Bit

Field name

Reset

Description

RFSR

0x0

Read-from-slave request. RFSR is set when a read-from-slave

"Slavetransmitter" request is received (I²C slave is addressed)

from the I²C line. On the assertion of this interrupt the TX FIFO

is flushed (pending data are cleared) and the CPU shall put

the data in TX FIFO. This bit is self-cleared by writing data in

FIFO. In case the FIFO is empty before the completion of the

read operation, the RISR:RFSE interrupt bit is set.This

interrupt is cleared by setting the related bit of the ICR

0: Read-from-slave request has been served.

1: Read-from-slave request is pending.

RFSE

0x0

Read-from-slave empty. RFSE is set when a read-from-slave

operation is in progress and TX FIFO is empty. On the

assertion of this interrupt, the CPU shall download in TX FIFO

the data required for the slave operation. This bit is self-

cleared by writing in TX FIFO. At the end of the read-from-

slave operation this bit is cleared although the TX FIFO is

empty.

0: TX FIFO is not empty.

1: TX FIFO is empty with the read-from-slave operation in

progress.

WTSR

0x0

Write-to-slave request. WTSR is set when a write-to-slave

operation is received (I2C slave is addressed) from the I2C

line. This notification can be used by the application to

program the DMA descriptor when required. This interrupt is

cleared by setting the related bit of the ICR register:

0: No write-to-slave request pending.

1: Write-to-slave request is pending.

MTD

0x0

Master transaction done. MTD is set when a master operation

(master write or master read) has been executed after a stop

condition. The application shall read the related transaction

status (SR register), the pending data in the RX FIFO (only for

a master read operation) and clear this interrupt (transaction

acknowledgment). A subsequent master operation can be

issued (writing the MCR register) after the clearing of this

interrupt. A subsequent slave operation will be notified

(RISR:WTSR and RISR:RFSR interrupt bits assertion) after

clearing this interrupt, meanwhile the I²C clock line will be

stretched low. This interrupt is cleared by setting the related

bit of the ICR register.

0: Master transaction acknowledged.

1: Master transaction done (ready for acknowledgment).

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