M16CSLASH26 datasheet(152/239 Pages) RENESAS

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UART2 Special Mode Register 2

146

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Bit 3 of the UARTi special mode register 2 are used as the SDAi output stop bit. Setting this bit to “1”

causes an arbitration loss to occur, and the SDAi pin turns to high-impedance state at the instant when

the arbitration lost detecting flag is set to “1”.

Bit 1 of the UART2 special mode register 2 are used as the clock synchronization bit. With this bit set to

“1” at the time when the internal SCL2 is set to “H”, the internal SCL2 turns to “L” if the falling edge is

found in the SCL2 pin; and the baud rate generator reloads the set value, and start counting within the “L”

interval.

When the internal SCL2 changes from “L” to “H” with the SCL2 pin set to “L”, stops counting the baud rate

generator, and starts counting it again when the SCL2 pin turns to “H”. Due to this function, the UART2

transmission-reception clock becomes the logical product of the signal flowing through the internal SCL2

and that flowing through the SCL2 pin. This function operates over the period from the moment earlier by

a half cycle than falling edge of the UART2 first clock to the rising edge of the ninth bit. To use this

function, choose the internal clock for the transfer clock.

Bit 2 of the UART2 special mode register 2 are used as the SCL2 wait output bit. Setting this bit to “1”

causes the SCL2 pin to be fixed to “L” at the falling edge of the ninth bit of the clock. Setting this bit to “0”

frees the output fixed to “L”.

Bit 4 of the UART2 special mode register 2 are used as the UART2 initialization bit. Setting this bit to “1”,

and when the start condition is detected, the microcomputer operates as follows.

(1) The transmission shift register is initialized, and the content of the transmission register is transferred

to the transmission shift register. This starts transmission by dealing with the clock entered next as the

first bit. The UART2 output value, however, doesn’t change until the first bit data is output after the

entrance of the clock, and remains unchanged from the value at the moment when the microcomputer

detected the start condition.

(2) The reception shift register is initialized, and the microcomputer starts reception by dealing with the

clock entered next as the first bit.

(3) The SCL2 wait output bit turns to “1”. This turns the SCL2 pin to “L” at the falling edge of the ninth bit

of the clock.

Starting to transmit/receive signals to/from UART2 using this function doesn’t change the value of the

transmission buffer empty flag. To use this function, choose the external clock for the transfer clock.

Bit 5 of the UART2 special mode register 2 are used as the SCL2 pin wait output bit 2. Setting this bit to

“1” with the serial I/O specified allows the user to forcibly output an “1” from the SCL2 pin even if UART2

is in operation. Setting this bit to “0” frees the “L” output from the SCL2 pin, and the UART2 clock is input/

output.

Bit 6 of the UART2 special mode register 2 are used as the SDA2 output disable bit. Setting this bit to “1”

forces the SDA2 pin to turn to the high-impedance state. Refrain from changing the value of this bit at the

rising edge of the UART2 transfer clock. There can be instances in which arbitration lost detecting flag is

turned on.

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