M16CSLASH26 datasheet(150/239 Pages) RENESAS

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Renesas Technology Corp.

UART2 Special Mode Register

144

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register)

CLK

TxD/RxD

Bus collision

detect interrupt

request bit

Transmit

enable bit

1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register)

0: Rising edges of the transfer clock

CLK

Timer A0

1: Timer A0 overflow

TxD/RxD

3. Transmit start condition select bit (Bit 6 of the UART2 special mode register)

CLK

TxD

Enabling transmission

CLK

TxD

RxD

With "1: falling edge of RxD2" selected

0: In normal state

Figure 1.15.29. Some other functions added

Some other functions added are explained here. Figure 1.15.29 shows their workings.

Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The

bus collision detect interrupt occurs when the RXD2 level and TXD2 level do not match, but the noncon-

formity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to “0”.

If this bit is set to “1”, the nonconformity is detected at the timing of the overflow of timer Aj rather than at

the rising edge of the transfer clock.

Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable

bit. Setting this bit to “1” automatically resets the transmit enable bit to “0” when “1” is set in the bus

collision detect interrupt request bit (nonconformity).

Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this bit

to “1” starts the TxD transmission in synchronization with the falling edge of the RxD terminal.

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