M16CSLASH26 datasheet(153/239 Pages) RENESAS

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UART2 Special Mode Register 3

147

Renesas Technology Corp.

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Function

SCL initial and last value

Transfer interrupt factor

Data transfer times from UART

receive shift register to receive

buffer register

CKPH = 0, IICM = 1, IICM2 = 1

Initial value = H, last value = L

Rising edge of 9th bit

Falling edge of 9th bit

CKPH = 1, IICM = 1, IICM2 = 1

Initial value = L, last value = L

Falling edge of 10th bit

Two times :falling edge of 9th bit

and rising edge of 9th bit

(2) CKPH= "1" (IICM=1, IICM2=1)

(1) CKPH= "0" (IICM=1, IICM2=1)

(Internal clock, transfer data 9 bits long and MSB first selected.)

SDA

SCL

Receive interrupt

Transmit interrupt

Transfer to receive buffer

(Internal clock, transfer data 9 bits long and MSB first selected.)

SDA

SCL

Receive interrupt

Transmit interrupt

Transfer to receive buffer

Figure 1.15.30. Functions changed by clock phase set bits

Bit 1 of UART2 special mode register 3 (address 037516) are used to clock phase set bit. Figure1.15.9

shows UART2 special mode register 3.

When both the IIC mode select bit (bit 0 of UART2 special mode select register) and the IIC mode select

bit 2 (bit 0 of U2SMR2 register) are “1”, functions changed by these bits are shown in table 1.15.16 and

figure 1.15.30.

Bits 5 to 7 of UART2 special mode register 3 are SDA digital delay setting bits. By setting these bits, it is

possible to turn the SDA delay OFF or set the BRG count source delay to 2 to 8 cycles.

Table 1.15.16. Functions changed by clock phase set bits

UART2 Special Mode Register 3

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