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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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M16C/26 датащи(PDF) 144 Page - Renesas Technology Corp |
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M16C/26 датащи(HTML) 144 Page - Renesas Technology Corp |
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144 / 239 page  Renesas Technology Corp. Clock Asynchronous Serial I/O (UART) Mode 138 M16C/26 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Under development Preliminary Specifications Rev. 0.9 Specifications in this manual are tentative and subject to change. Figure 1.15.24. Typical transmit/receive timing in UART mode (used for SIM interface) fi : frequency of BRG2 count source (f1SIO, f2SIO, f8SIO, f32SIO) fi : frequency of BRG2 count source (f1SIO, f2SIO, f8SIO, f32SIO) Transmit enable bit(TE) Transmit buffer empty flag(TI) Transmit register empty flag (TXEPT) D0 D1 D2 D3 D4 D5 D6 D7 ST P Start bit Parity bit The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = 1 . 0 1 0 1 0 1 Tc = 16 (n + 1) / fi n : value set to BRG2 Transmit interrupt request bit (IR) 0 1 D0 D1 D2 D3 D4 D5 D6 D7 ST P Shown in ( ) are bit symbols. Tc Transfer clock SP Stop bit Data is set in UART2 transmit buffer register SP An L level returns from TxD2 due to the occurrence of a parity error. The level is detected by the interrupt routine. The level is detected by the interrupt routine. Receive enable bit (RE) Receive complete flag (RI) D0 D1 D2 D3 D4 D5 D6 D7 ST P Start bit Parity bit RxD2 The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = 0 . 0 1 0 1 Tc = 16 (n + 1) / fi n : value set to BRG2 Receive interrupt request bit (IR) 0 1 D0 D1 D2 D3 D4 D5 D6 D7 ST P SP Shown in ( ) are bit symbols. Tc Transfer clock SP Stop bit An L level returns from TxD2 due to the occurrence of a parity error. TxD2 Read to receive buffer Read to receive buffer D0 D1 D2 D3 D4 D5 D6 D7 ST P Signal conductor level (Note) D0 D1 D2 D3 D4 D5 D6 D7 ST P SP SP D0 D1 D2 D3 D4 D5 D6 D7 ST P D0 D1 D2 D3 D4 D5 D6 D7 ST P SP SP TxD2 RxD2 Signal conductor level (Note) Note : Equal in waveform because TxD2 and RxD2 are connected. Transferred from UART2 transmit buffer register to UART2 transmit register Cleared to 0 when interrupt request is accepted, or cleared by software Cleared to 0 when interrupt request is accepted, or cleared by software Note : Equal in waveform because TxD2 and RxD2 are connected. |
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