M16CSLASH26 datasheet(143/239 Pages) RENESAS

143 / 239 page

Renesas Technology Corp.

Clock Asynchronous Serial I/O (UART) Mode

137

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Clock-Asynchronous Serial I/O Mode (used for SIM interface)

The SIM (Subscriber Identity Module) interface is used for connecting the microcomputer with a memory

card or the like; adding some extra settings in UART2 clock-asynchronous serial I/O mode allows the user

to use this function. Table 1.15.12 shows the specifications of clock-asynchronous serial I/O mode (used

for SIM interface).

Table 1.15.12. Specifications of clock-asynchronous serial I/O mode (used for SIM interface)

Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UART2 bit rate generator.

Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. In addition, the

UART2 receive interrupt request bit does not change.

Specification

Item

Transfer data format

Transmission/reception control

Transfer clock

Set data logic to “direct” (bit 6 of address 037D16 = “0”)

Other settings

Set data logic to “inverse” (bit 6 of address 037D16 = “1”)

Transmission start condition

Interrupt request

generation timing

Error detection

• Set transmission interrupt factor to “transmission completed” (bit 4 of

address 037D16 = “1”)

• When receiving

Set parity to “even” (bit 5, bit 6 of address 037816 = “112”)

• Transfer data 8-bit UART mode (bit 2, bit1, bit 0 of address 037816 = “1012”)

• One stop bit (bit 4 of address 037816 = “0”)

• With the direct format chosen

• Framing error (see the specifications of clock-asynchronous serial I/O)

- Transmit buffer empty flag (bit 1 of address 037D16) = “0”

Set transfer format to LSB (bit 7 of address 037C16 = “0”)

Set parity to “odd” (bit 5, bit 6 of address 037816 = “012”)

• Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2)

When data transfer from the UART2 receive register to the UART2 receive

buffer register is completed

- Detection of a start bit

• Disable the CTS and RTS function (bit 4 of address 037C16 = “1”)

Set transfer format to MSB (bit 7 of address 037C16 = “1”)

• With the internal clock chosen (bit 3 of address 037816 = “0”) : fi / 16 (n + 1)

(Note 1) : fi = f1SIO, f2SIO, f8SIO, f32SIO (Do not set external clock)

- Reception enable bit (bit 2 of address 037D16) = “1”

• To start transmission, the following requirements must be met:

Reception start condition

• UART2 does not support sleep mode function.

• To start reception, the following requirements must be met:

• When transmitting

When data transmission from the UART2 transmit register is completed

(bit 4 of address 037D16 = “1”)

- Transmit enable bit (bit 0 of address 037D16) = “1”

• With the inverse format chosen

• Parity error (see the specifications of clock-asynchronous serial I/O)

- On the reception side, an “L” level is output from the TXD2 pin by use of

the parity error signal output function (bit 7 of address 037D16 = “1”)

when a parity error is detected

- On the transmission side, a parity error is detected by the level of input to

the RXD2 pin when a transmission interrupt occurs

• The error sum flag (see the specifications of clock-asynchronous serial I/O)

M16C/26 датащи(PDF) 143 Page - Renesas Technology Corp

M16C/26 датащи(HTML) 143 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL