M16CSLASH26 datasheet(140/239 Pages) RENESAS

140 / 239 page

Renesas Technology Corp.

Clock Asynchronous Serial I/O (UART) Mode

134

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)

Figure 1.15.20. Typical transmit timing in UART mode (UART2)

• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)

Figure 1.15.21. Typical receive timing in UART mode

Start bit

Sampled L

Receive data taken in

BRGi count

source

Receive enable bit

RxDi

Transfer clock

Receive

complete flag

RTSi

Stop bit

The above timing applies to the following settings :

* Parity is disabled.

* One stop bit.

* RTS function is selected.

Receive interrupt

request bit

Transferred from UARTi receive register to

UARTi receive buffer register

Reception triggered when transfer clock

is generated by falling edge of start bit

Cleared to 0 when interrupt request is accepted, or cleared by software

fi : frequency of BRG2 count source (f1SIO, f2SIO, f8SIO, f32SIO)

D0 D1

D2 D3 D4 D5 D6 D7

Start

bit

Parity

bit

Cleared to 0 when interrupt request is accepted, or cleared by software

D0 D1 D2 D3 D4 D5 D6 D7

Stop

bit

Data is set in UART2 transmit buffer register

Transferred from UART2 transmit buffer register to UARTi transmit register

Transmit enable

bit(TE)

Transmit buffer

empty flag(TI)

Transmit register

empty flag (TXEPT)

Transmit interrupt

request bit (IR)

Transfer clock

TxD2

The above timing applies to the following settings :

* Parity is enabled.

* One stop bit.

* Transmit interrupt cause select bit = 1 .

Tc = 16 (n + 1) / fi

n : value set to BRG2

Shown in ( ) are bit symbols.

Note

Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.

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