M16CSLASH26 datasheet(138/239 Pages) RENESAS

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Renesas Technology Corp.

Clock Asynchronous Serial I/O (UART) Mode

132

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Under

development

Preliminary Specifications Rev. 0.9

Specifications in this manual are tentative and subject to change.

Table 1.15.10 lists the functions of the input/output pins during UART mode. Note that for a period

from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”.

(If the N-channel open-drain is selected, this pin is in floating state.)

Table 1.15.10. Input/output pin functions in UART mode

Pin name

Function

Method of selection

TxDi

(P63, P67, P70)

Serial data output

Serial data input

Programmable I/O port

Transfer clock input

Programmable I/O port

RxDi

(P62, P66, P71)

CLKi

(P61, P65, P72)

Internal/external clock select bit (bit 3 of address 03A016, 03A816, 037816) = 0

Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = 1

Port P61, P65 and P72 direction register (bits 1 and 5 of address 03EE16) = 0

(Do not use external for UART2)

Port P62, P66 and P71 direction register (bits 2 and 6 of address 03EE16,

bit 1 of address 03EF16)= 0

(Can be used as an input port when performing transmission only)

CTS/RTS disable bit (bit 4 of address 03A416, 03AC16, 037C16) = 0

CTS/RTS function select bit (bit 2 of address 03A416, 03AC16, 037C16) = 0

Port P60, P64 and P73 direction register (bits 0 and 4 of address 03EE16,

bit 3 at address 03EF16) = 0

CTS/RTS disable bit (bit 4 of address 03A416, 03AC16, 037C16) = 0

CTS/RTS function select bit (bit 2 of address 03A416, 03AC16, 037C16) = 1

CTS/RTS disable bit (bit 4 of address 03A416, 03AC16, 037C16) = 1

CTS input

RTS output

CTSi/RTSi

(P60, P64, P73)

Table 1.15.11. P64 pin function in UART mode

Pin function

Bit set value

U1C0 register

UCON register

PD6 register

CRD

CRS

RCSP

CLKMD1

PD6_4

P64

Input: 0, Output: 1

CTS1

RTS1

CTS0 (Note)

Note: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS0/RTS0

enabled) and the U0C0 register’s CRS bit to “1” (RTS0 selected).

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