USB97C102 datasheet(73/80 Pages) SMSC

73 / 80 page

SMSC DS – USB97C102

Page 73

Rev. 03/23/2000

PARAMETER

SYM

CONDITIONS

(NOTE 1, 2, 3)

MIN

TYP

MAX

UNIT

CABLE IMPEDANCE AND TIMING:

Cable Impedance (Full

Speed)

(45 $ +/- 15%)

38.75

51.75

Cable Delay (One Way)

TCBL

FIGURE 11

Note 1: All voltages are measured from the local ground potential, unless otherwise specified.

Note 2: All timing use a capacitive load (CL) to ground of 50pF, unless otherwise specified.

Note 3: Full speed timings have a 1.5K$ pull-up to 2.8 V on the D+ data line.

Note 4: Measured from 10% to 90% of the data signals.

Note 5: The rising and falling edges should be smoothly transiting (monotonic).

Note 6: Timing differences between the differential data signals.

Note 7: Measured at crossover point of differential data signals.

Note 8: These are relative to the 24 MHz crystal.

FIGURE 15 - 8051 IO WRITE CYCLE

Table 122 – 8051 IO Write Cycle

NAME

DESCRIPTION

MIN

MAX

EQUIATION

UNITS

SA[x] and AEN Valid to nIOW Asserted

106

4t-60

nIOW Asserted to nIOW Deasserted

150

6t-100

nIOW Deasserted to SA[x] Invalid

t-20

SD[x] Valid to nIOW Deasserted

150

6t-100

SD[x] Hold from nIOW Deasserted

t-20

nIOW Deasserted to nIOW Asserted

nIOW Deasserted to AEN Deasserted

t-20

nIOW Deasserted to SD[x] tri-state

Note:

Min and Max delays shown for 8051 clock of 24 MHz, to calculate typical timing delays for other

clock frequencies use Oscillator Equations, where t=1/fCLK.

DATA VALID

AEN

SA[x]

nIOW

SD[x]

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