USB97C102 datasheet(62/80 Pages) SMSC

62 / 80 page

SMSC DS – USB97C102

Page 62

Rev. 03/23/2000

Table 113 – IN_NAKLO Register

IN_NAKLO

(0x7FEC – RESET=0x00)

IN_NAKLO REGISTER

BIT

NAME

R/W

DESCRIPTION

IN_NAK_7

R/W

This bit is set when the SIE responds with a NAK to IN

tokens on EP 7 and reset when the MCU writes a ‘1’ to it.

IN_NAK_6

R/W

This bit is set when the SIE responds with a NAK to IN

tokens on EP 6 and reset when the MCU writes a ‘1’ to it.

IN_NAK_5

R/W

This bit is set when the SIE responds with a NAK to IN tokens

on EP 5 and reset when the MCU writes a ‘1’ to it.

IN_NAK_4

R/W

This bit is set when the SIE responds with a NAK to IN tokens

on EP 4 and reset when the MCU writes a ‘1’ to it.

IN_NAK_3

R/W

This bit is set when the SIE responds with a NAK to IN tokens

on EP 3 and reset when the MCU writes a ‘1’ to it.

IN_NAK_2

R/W

This bit is set when the SIE responds with a NAK to IN tokens

on EP 2 and reset when the MCU writes a ‘1’ to it.

IN_NAK_1

R/W

This bit is set when the SIE responds with a NAK to IN tokens

on EP 1 and reset when the MCU writes a ‘1’ to it.

IN_NAK_0

R/W

This bit is set when the SIE responds with a NAK to IN tokens

on EP 0 and reset when the MCU writes a ‘1’ to it.

Table 114 – IN_NAKHI Register

IN_NAKHI

(0x7FED – RESET=0x00)

IN_NAKHI REGISTER

BIT

NAME

R/W

DESCRIPTION

IN_NAK_15

R/W

This bit is set when the SIE responds with a NAK to IN

tokens on EP 15 and reset when the MCU writes a ‘1’ to it.

IN_NAK_14

R/W

This bit is set when the SIE responds with a NAK to IN

tokens on EP 14 and reset when the MCU writes a ‘1’ to it.

IN_NAK_13

R/W

This bit is set when the SIE responds with a NAK to IN tokens

on EP 13 and reset when the MCU writes a ‘1’ to it.

IN_NAK_12

R/W

This bit is set when the SIE responds with a NAK to IN tokens

on EP 12 and reset when the MCU writes a ‘1’ to it.

IN_NAK_11

R/W

This bit is set when the SIE responds with a NAK to IN tokens

on EP 11 and reset when the MCU writes a ‘1’ to it.

IN_NAK_10

R/W

This bit is set when the SIE responds with a NAK to IN tokens

on EP 10 and reset when the MCU writes a ‘1’ to it.

IN_NAK_9

R/W

This bit is set when the SIE responds with a NAK to IN tokens

on EP 9 and reset when the MCU writes a ‘1’ to it.

IN_NAK_8

R/W

This bit is set when the SIE responds with a NAK to IN tokens

on EP 8 and reset when the MCU writes a ‘1’ to it.

Table 115 – OUT_NAKLO Register

OUT_NAKLO

(0x7FEE – RESET=0x00)

OUT_NAKLO REGISTER

BIT

NAME

R/W

DESCRIPTION

OUT_NAK_7

R/W

This bit is This bit is set(1) when after the SIE responds with

a NAK to OUT tokens on EP 7 and reset(0) after when the

MCU writes a ‘1’ to it.

OUT_NAK_6

R/W

This bit is set(1) when after the SIE responds with a NAK to

OUT tokens on EP 6 and reset(0) when after the MCU writes

a ‘1’ to it.

OUT_NAK_5

R/W

This bit is set

(1) when the SIE responds with a NAK to OUT

tokens on EP 5 and reset

(0) when after the MCU writes a ‘1’ to

it.

OUT_NAK_4

R/W

This bit is set

(1) when the SIE responds with a NAK to OUT

tokens on EP 4 and reset

(0) when after the MCU writes a ‘1’ to

it.

OUT_NAK_3

R/W

This bit is set

(1) when the SIE responds with a NAK to OUT

tokens on EP 3 and reset

(0) when after the MCU writes a ‘1’ to

it.

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