USB97C102 datasheet(59/80 Pages) SMSC

59 / 80 page

SMSC DS – USB97C102

Page 59

Rev. 03/23/2000

This register allows the individual setting and clearing of the bits in the EP_CTRL registers.

Table 107 - Endpoint Command Register

EP_COMM

(0x7FAA- RESET=0x00)

ENDPOINT Command Register

BIT

NAME

R/W

DESCRIPTION

TX/RX

R/W

This bit, when set (1) will allow the command specified in bits 6-4

to control the TX endpoint. When this bit is cleared (0), the

command control the RX endpoint. In other words, if set (1), the

command will affect TX_ISO, TX_ENABLE, STALL_TXEP, and

TX_TOGGLE (defined in EPCTRL). If clear (0), the command will

affect RX_ISO, RX_ENABLE, STALL_RXEP, and RX_TOGGLE

(also defined in EPCTRL).

5 4

COMMAND BITS

0 0

Endpoint is disabled, and does not send handshakes.

0 1

Send a STALL handshake for an IN and/or OUT

transaction directed at this EP.

1 0

Normal Operation. ACK or NAK is sent depending on

whether data is in the EPXs TX_QUEUE or conversely for

EPX’s receive transactions.

1 1

Send a NAK handshake for an IN and/or OUT transaction

directed at this EP, regardless of TX_QUEUE status.

0 0

Clear Tx / Rx Toggle bit

0 1

Set Tx / Rx Toggle bit

1 0

Clear Tx / Rx ISO bit

[6:4]

COMMAND

R/W

1 1

Set Tx / Rx ISO bit

EP_COMM

(0x7FAA- RESET=0x00)

ENDPOINT Command Register

BIT

NAME

R/W

DESCRIPTION

2 1

ENDPOINT SELECT

0 0

Endpoint 0

0 0

Endpoint 1

0 1

Endpoint 2

0 1

Endpoint 3

1 0

Endpoint 4

1 0

Endpoint 5

1 1

Endpoint 6

1 1

Endpoint 7

0 0

Endpoint 8

0 0

Endpoint 9

0 1

Endpoint 10

0 1

Endpoint 11

1 0

Endpoint 12

1 0

Endpoint 13

1 1

Endpoint 14

[3:0]

EP_Select

R/W

1 1

Endpoint 15

Section 8.4.5.4 of the USB Spec V1.1 states that “If a non-control endpoint receives a SETUP PID, it must ignore the

transaction and return no response.” In order for the hardware to do this correctly, it needs to know which endpoints

are non-control endpoints.

Each bit of the NonControl Endpoint registers will correspond to the associated Endpoint. Bits 0-7 of the NonControl

Endpoint 1 register will correspond to Endpoints 7-15. Bits 0-7 of the NonControl Endpoint 2 will correspond to

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