USB97C102 datasheet(57/80 Pages) SMSC

57 / 80 page

SMSC DS – USB97C102

Page 57

Rev. 03/23/2000

Table 103 - SIE Status Register

SIE_STAT

(0x7F93 - RESET=0x03)

SIE STATUS REGISTER

BIT

NAME

R/W

DESCRIPTION

ERR

Indicates that an error occurred during the last USB

transaction. Considered valid on the rising edge of EOT

TIMEOUT

Indicate that the last USB transaction ended because of an

inter-packet time out condition (i.e.:>16 bit times).

Considered valid on the rising edge of EOT.

SETUP_TOKEN

Indicates that the token received was a SETUP token.

SOF_TOKEN

Indicates that the SOF PID has been received. Considered

valid when EOT is '0'.

PRE_TOKEN

Indicates that the SIE detected a PRE (preamble) packet on

the USB bus. The signal is asserted when the SIE has seen

a valid SYNC followed by a valid PRE PID.

ACK

Indicates that the last USB transaction was completed

without error or time-out. Considered valid on the rising

edge of EOT.

USB_RESET

When active '1', it indicates that the USB line is being reset.

This signal is asserted when the SIE detects a string of

single – ended 0's on the bus for a long time.

[During USB_RESET, this bit is set(1). When the firmware

sends a system reset, this bit is cleared(0)]

EOT

End - of - Transaction. On transition to a '1', it indicates the

end of transaction. On transition to a '0' it indicates the

beginning of a new transaction.

Note:

This read only register reflects the status signals from the SIE state machine. This register can be polled for

test purposes, or by error handling routines for recovery.

Table 104 - SIE Control Register 1

SIE_CTRL1

(0x7F94 - RESET=0x00)

SIE CONTROL REGISTER 1

BIT

NAME

R/W

DESCRIPTION

SIEDMA_DISABLE

R/W

0 = Normal operation

1 = Inhibits SIEDMA operation to facilitate MCU override

FORCE_RXOK

R/W

Forces SIE to send Acknowledge during receive. Must be

'0' for normal operation.

FORCE_TTAG

R/W

0 = Normal operation

1 = Signals that the next byte written to the SIE TX_FIFO is

the last payload byte.

FORCE_RXOVFLO

R/W

0 = Normal operation.

1 = Forces the SIE to generate RXOVFLO and clear the

SIE RX FIFO.

FORCE_TXABORT

R/W

0 = Normal operation

1 = Forces a bit-stuff error at the host

FORCE_EOT

R/W

0 = Normal operation

1 = Forces an End-of-Transaction for the SIE

RTAG_IN

Status of RTAG signal from SIE RX FIFO

TXOK_IN

Status of TXOK from SIE

Note:

Bits 7:2 must be set to “0” for normal operation. Altering these bits will cause an abnormal USB behavior.

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