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USB97C102 датащи(PDF) 45 Page - SMSC Corporation |
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USB97C102 датащи(HTML) 45 Page - SMSC Corporation |
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45 / 80 page ![]() SMSC DS – USB97C102 Page 45 Rev. 03/23/2000 Table 80 - Pointer Register (High) PRH (0x7F51) POINTER REGISTER (HIGH) BIT NAME R/W DESCRIPTION 7 RCV R/W 0 = The packet at 0x6000 is the packet pointed to by the PNR register. 1 = The packet available at 0x6000 is the packet pointed to by the packet on the top of the RX Packet Number FIFO. 6 AUTO_INCR R/W 0 = Auto-increment is disabled 1 = Causes the PRH:PRL register to be automatically incremented each time the 0x6000 data window is accessed. 5 READ R/W Data register direction. This bit is required for the MMU/Arbiter to provide a transparent interface to the buffer RAM for the MCU. When first set, the MMU immediately fills the read FIFO. The MCU must wait 2.5us (60 Arbiter clocks) after writing to the MMU_DATA register before changing this bit from '0' to '1'. 0 = WRITE 1 = READ [4:3] Reserved R Reserved [2:0] A[10:8] R/W MSB of the (0-1277 Max) offset of the allocated Packet Pointed to by PNR. The byte(s) pointed to by this register can be read and written to by the MCU at 0x6000. Note: This register must be written after PRL for its value to take effect. Table 81 - Transmit FIFO Select Register MMUTX_SEL (0x7F52) TRANSMIT FIFO SELECT REGISTER BIT NAME R/W DESCRIPTION [7:4] Reserved R Reserved [3:0] EP[3:0] R/W This register selects which Endpoint Commands "110" and "111" will affect when issued to the MMU Note: This register must be written before writing the “Enqueue Packet into Endpoint x” or the “Reset TX Endpoint x” command to the MMUCR. Table 82 - MMU Command Register MMUCR (0x7F53) MMU COMMAND REGISTER BIT NAME R/W DESCRIPTION [7:5] MMU_CMD W MMUCR COMMAND SET 4 Reserved W Reserved, writes are ignored and read return “0” [3:0] N[3:0] W Number of 128 byte Pages. N[3..0]=0000 indicates 1 page, and N[3..0]=1001 indicates 10 pages, or 1280 bytes. |
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