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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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USB97C102 датащи(PDF) 48 Page - SMSC Corporation |
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USB97C102 датащи(HTML) 48 Page - SMSC Corporation |
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48 / 80 page  SMSC DS – USB97C102 Page 48 Rev. 03/23/2000 Table 87 - Receive Packet Number FIFO Register RXFIFO (0x7F58) NEXT RX PACKET NUMBER FIFO REGISTER BIT NAME R/W DESCRIPTION 7 RXFIFO_EMPTY R 1 = No pending packets from the host to be processed 6 RXFIFO_FULL R 1 = The SIEDMA will not accept packets from the host (via RX Overflow) 5 Reserved R Reserved [4:0] P[4:0] R Packet Number When a packet has been received, and the 8-byte header has been written by the SIEDMA, the associated Packet Number is placed in this FIFO. A "complete" reception requires that the 8 byte status header is correctly written into the packet buffer, with the correct data, and moved into the RX Packet Number FIFO. A "successful" reception requires that the CRC and PID check bits of a "complete" reception are good. The hardware queues only "complete" packets. Firmware must determine if "complete" packets were "successful". Corrupted token packets causes the complete data payload to be ignored. |
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