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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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USB97C102 датащи(PDF) 58 Page - SMSC Corporation |
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USB97C102 датащи(HTML) 58 Page - SMSC Corporation |
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58 / 80 page  SMSC DS – USB97C102 Page 58 Rev. 03/23/2000 Table 105 - SIE Configuration Register. SIE_CONFIG (0x7F98 - RESET=0x40) SIE CONFIGURATION REGISTER BIT NAME R/W DESCRIPTION 7 FSEN R/W This bit indicates that the USB97c102 supports 12Mbps USB data rates. This bit must be set to a one ‘1’ for normal operation. 6 RST_SIE R/W 1 = Resets the SIE 5 RST_FRAME R/W 1 = Clears FRAMEL and Bit 0 through 2 of FRAMEH 4 EN_EXTFRAME R/W Extended Frame Count Enable. Expands the Frame count from 11 bits to 16 bits for 8051 use. 0 = Bits 7-3 of FRAMEH are driven to 0. 1 = Bits 7-3 of FRAMEH count 1-0 transitions of bit 2 in FRAMEH. 3 SIE_SUSPEND R/W 1 = Forces the SIE into USB Suspend Mode. The MCU must determine that Suspend must be entered. 2 SIE_RESUME R/W 1 = Forces the SIE to transmit Resume signaling on the line. 1 USB_RESUME R 1 = Indicates Resume signaling has been detected on the line while in the Suspend State. This signal causes a Resume Power Management interrupt). 0 USB_RESET R 1 = Indicates that the USB line is being reset. Asserted when SE0 is present on the bus for 32 or more 12 Mbps bit times. This causes a USB_RESET Power management interrupt. Table 106 - SIE Control Register 2 SIE_CTRL 2 (0x7FA9 – RESET=0x00) SIE CONTROL REGISTER 2 BIT NAME R/W DESCRIPTION 7 Reserved R/W Reserved – This bit should always be cleared (0) 6 Reserved R/W Reserved – This bit should always be cleared (0) 5 Reserved R/W Reserved – This bit should always be cleared (0) 4 Reserved R/W Reserved – This bit should always be cleared (0) 3 Reserved R/W Reserved – This bit should always be cleared (0) 2 SET_BUSY_ON_SETU P R/W When set (1), a setup pckt rcvd on a control endpoint will set that endpoint to busy in any direction it was not disabled. When clear (0), a setup pckt will have no effect on the endpoint’s control condition. ISO_Limit – Defines the maximum size of an isochronous packet 1 0 PAYLOAD SIZE 0 0 1023 byte payload 0 1 248 byte payload total less 8 byte header = 240 byte Data payload 1 0 504 byte payload total less 8 byte header = 496 byte Data payload [1:0] ISO_LIMIT R/W 1 1 248 byte payload total less 8 byte header = 240 byte Data payload In conjunction with the Endpoint Control Registers defined above, the Endpoint Command Register allows the dynamic modification and configuration of specific endpoints. This register which is new to the SMSC Family of USB devices, allows the MCU to write each individual bit field within the existing register Endpoint set without having to do read / modify / write operations. The Firmware can jam this register with a full constant, or could OR-in an EP number. |
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