USB97C102 datasheet(49/80 Pages) SMSC

49 / 80 page

SMSC DS – USB97C102

Page 49

Rev. 03/23/2000

Tx FIFO POP Register

This register is used to help software manage TX Queues.

This will provide a method to handle a

CLEAR_FEATURE:ENDPOINT_STALL condition gracefully. When read, this register will return the Packet Number

of the next packet waiting on the TX queue pointed to by MMUTX_SEL register, AND it will pop that Packet Number

off of the selected TX FIFO.

Table 88 - POP TX FIFO

POP_TX

(0x7F59 – RESET=0x80)

POP TX FIFO

BIT

NAME

R/W

DESCRIPTION

POPTX_STAT

POP TX FIFO empty status

0 = Has one or more TX packet

1 = Empty

[6:5]

Reserved

[4:0]

POP_TX

This 5 bit value is the packet number or handle that is at the top of

the TX FIFO pointer to by MMUTX_SEL. The TX FIFO is popped

when this register is read.

Note: It is the software's responsibility to ensure that the appropriate TX EP is disabled during this operation, and to

issue a de-allocate command if desired.

Table 89 - Transmit FIFO Status Register A

TXSTAT_A

(0x7F60 - RESET=0x55)

TRANSMIT FIFO STATUS REGISTER A

BIT

NAME

R/W

DESCRIPTION

EP3TX_EMPTY

Endpoint 3 Transmit Packet FIFO Status

Bits [7:6]='11' Invalid

Bits [7:6]='10' Empty (No Packets queued)

Bits [7:6]='01' Full (5 Packets queued)

Bits [7:6]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP3TX_FULL

EP2TX_EMPTY

Endpoint 2 Transmit Packet FIFO Status

Bits [5:4]='11' Invalid

Bits [5:4]='10' Empty (No Packets queued)

Bits [5:4]='01' Full (5 Packets queued)

Bits [5:4]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP2TX_FULL

EP1TX_EMPTY

Endpoint 1 Transmit Packet FIFO Status

Bits [3:2]='11' Invalid

Bits [3:2]='10' Empty (No Packets queued)

Bits [3:2]='01' Full (5 Packets queued)

Bits [3:2]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP1TX_FULL

EP0TX_EMPTY

Endpoint 0 Transmit Packet FIFO Status

Bits [1:0]='11' Invalid

Bits [1:0]='10' Empty (No Packets queued)

Bits [1:0]='01' Full (5 Packets queued)

Bits [1:0]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP0TX_FULL

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