USB97C102 datasheet(33/80 Pages) SMSC

33 / 80 page

SMSC DS – USB97C102

Page 33

Rev. 03/23/2000

Runtime Registers

The DMA controller has a block of 16 R/W registers which normally occupy I/O locations 0x00-0x0F on the ISA bus.

When they are located at 0x0000-0x000F on the ISA bus, the 8051 can access them by programming the IOBASE

Table 42 - 8237 Registers in ISA I/O Space

0x0000

Channel 0: Current Address H/L

0x0001

Channel 0: Byte Count H/L

0x0002

Channel 1: Current Address H/L

0x0003

Channel 1: Byte Count H/L

0x0004

Channel 2: Current Address H/L

0x0005

Channel 2: Byte Count H/L

0x0006

Channel 3: Current Address H/L

0x0007

Channel 3: Byte Count H/L

0x0008

Status/Command Register

0x0009

Write Request Register

0x000A

Write Single Mask Register

0x000B

Write Mode Register

0x000C

Clear Byte Ptr F/F - Read Temp Register

0x000D

Master Clear

0x000E

Clear Mask

0x000F

Write All Mask Bits

Note: To write to these registers, HLDA must be logic low.

Table 43 - 8237 Address Programming Guide

8237 INTERNAL ADDRESS PROGRAMMING GUIDE

BIT

NAME

DESCRIPTION

INT_EXT

Indicates whether this address refers to Internal Buffer RAM or

External ISA Memory Space

0 = External

1 = Internal

When this bit is set to zero (0), I/O capability is added to External

Memory DMA. This capability can only be used for DMA channels 2

or 3.

[14:10]

PN[4:0]/SA[14:10]

External Address -or- Internal Packet Number

SA[14..10] when INT_EXT=0

PN[4..0] when INT_EXT=1

[9:0]

PTR[9:0]/SA[9:0]

External Address -or- Internal Packet Offset Pointer

SA[9..0] when INT_EXT=0

PTR[9..0] when INT_EXT=1

Note: SA[19..15] are driven low when the 8237 is accessing external ISA memory. PTR10 is driven low when the

8237 is accessing internal buffer RAM. Note that the actual transfer size for the ISADMA is limited to 1024

bytes, which limits the payload data to 1016 bytes per transfer when the 8 byte header is skipped. Also note

that the 8051 still has access to 1Meg of external RAM through the MEMBASE register and it is independent

of the 8237's 32k external limit.

Table 44 - Channel 0 Current Address Register

CH0_ADDR

(ISA 0x0000)

CHANNEL 0 CURRENT ADDRESS

BIT

NAME

R/W

DESCRIPTION

[7:0]

CH0_ADDRL

R/W

Lower 8 bits of Base and Current Address when Byte F/F = 0

[7:0]

CH0_ADDRH

R/W

Upper 8 bits of Base and Current Address when Byte F/F = 1

Note: Byte F/F is an internal Flip Flop which reflects which byte (high or low) is being written. The CLEAR_FF

See the Address Programming Table for 16 bit Address definitions.

USB97C102 датащи(PDF) 33 Page - SMSC Corporation

USB97C102 датащи(HTML) 33 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

датащи скачать

ссылки URL