USB97C102 datasheet(41/80 Pages) SMSC

41 / 80 page

SMSC DS – USB97C102

Page 41

Rev. 03/23/2000

SGDMA_STSx [x=0..3]

(BASE+8 – RESET = 0x00)

SGDMA_STS

BIT

NAME

DESCRIPTION

START_FIFO_FULLx

[x=0..3]

Set(1) when SGDMA_START_FIFOx [x=0..3] is full

Clear(0) when SGDMA_START_FIFOx [x=0..3] is not full

START_FIFO_EMPTY

[x=0..3]

Set(1) when SGDMA_START_FIFOx [x=0..3] is empty

Clear(0) when SGDMA_START_FIFOx [x=0..3] is not not

empty

Table 71 – SGDMA Command Register

SGDMA_CMDx [x=0..3]

(BASE+9 – RESET = 0x00)

SGDMA_CMD

BIT

NAME

R/W

DESCRIPTION

[7:3]

Reserved

R/W

Reserved – Read back as 0

PCKT_HD

R/W

Set(1) to indicate that a packet header is present. Clear(0) to

indicate that there is no packet header. Applies only if MEM_OP

is set(1).

MEM_OP

R/W

Set(1) to indicate a MMU memory operation. Clear(0) to indicate

an ISA memory operation.

When clear(0), the packet size comes from the

SGDMA_SIZEHIx/LOx [x=0..3] registers, whose value is

decremented before being written into the 8237 count

SGDMA_ADHIx/LOx [x=0..3] registers.

When set(1), and PCKT_HDR=0, the packet size comes

from the SGDMA_SIZEHIx/LOx [x=0..3] registers, whose

value is decremented before being written into the 8237

count register. The High byte of the address is based on the

packet number, and the low byte of the address is 0.

When set(1), and PCKT_HDR=1, the high byte of the

address is based on the packet number and the low byte of

the address is 8.

For a MemRd transfer, the packet size is read from the

packet header – this value represents the number of bytes

of payload data plus header, so this value minus 9 is written

into the 8237 counter register. If the packet size in the

header is 8 (indicating a zero-byte payload), no DMA

transfer will occur but the SGDMA will but the packet

number into the SGDMA_DONE_FIFOx [x=0..3].

For a MemWr transfer, the SGDMA_SIZEHIx/LOx [x=0..3]

registers contain the number of bytes of payload data, so

this value is decremented before being written into the 8237

count register, and this value plus 8 is written into the packet

memory at an offset of 6.

CHANNEL

_ENABLE

R/W

Set(1) to enabled the channel. Clear(0) to disable the channel. If

this bit is cleared during a SGDMA cycle (before TC), then:

If MEM_OP=1, the packet number is put into the

SGDMA_DONE_FIFOx [x=0..3] and the SGDMA returns to

idle, ready for another cycle.

If MEM_OP=0, the SGDMA returns to idle and is ready for

another cycle.

If a memory-to-memory transfer, the packet number for the

MMU channel is put into the SGDMA_DONE_FIFO0x [0 or

1], but none of the updates to the address or size register

occur, and the SGDMA returns to idle and is ready for

another cycle.

Note 1: The PKT_HDR and MEM_OP bits must not be changed unless the channel is disabled

(CHANNEL_ENABLRE=0 in register SGDMA_CMDx [x=0..3]) and not busy (DMA_BUSY=0 in

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