USB97C102 datasheet(19/80 Pages) SMSC

19 / 80 page

SMSC DS – USB97C102

Page 19

Rev. 03/23/2000

ADDRESS

NAME

R/W

DESCRIPTION

PAGE

HUB REGISTERS

7FA5

BcdDevice - High

Byte

R/W

This 8-bit value defines the USB device

release number, which is assigned by

the system manufacture.

7FA6

HubControl1

R/W

Hub Control register 1

MCU REGISTER DESCRIPTION

MCU Runtime Registers

Table 11 - Interrupt 0 Source Register

ISR_0

(0x7F00 - RESET=0x00)

INTERRUPT 0 SOURCE REGISTER

BIT

NAME

R/W

DESCRIPTION

IRQ3

R/W

External interrupt input.

0 = Inactive

1 = Active

IRQ2

R/W

External interrupt input.

0 = Inactive

1 = Active

IRQ1

R/W

External interrupt input.

0 = Inactive

1 = Active

IRQ0

R/W

External interrupt input.

0 = Inactive

1 = Active

RX_PKT

R/W

1 = A Packet Number (PNR) has been successfully queued on

the RXFIFO.

TX_EMPTY

R/W

1 = Whenever an enabled TX Endpoint's FIFO becomes

empty. This will occur when the last queued packet in one of

the 16 TX queues is successfully transferred to the Host.

TX_PKT

R/W

1 = A Packet was successfully transmitted.

ISADMA

R/W

1 = When a selected 8237 channels in

BUS_STAT/BUS_MASK register pair either reached Terminal

Count or have a new DMA Request Pending.

The bits in this register are cleared by writing a ‘1’ to the corresponding bit.

Note 1: TX_EMPTY is useful for warning of USB performance degradation. This interrupt indicates that the next time

the Host polls the affected endpoint, it will receive a NAK for that endpoint, thus reducing effective overall

bandwidth due to retries. Firmware must use TX_STAT A, B, and C to determine which endpoint queue is

empty.

Note 2: When ISADMA causes an interrupt, the 8237 CH_STAT register should also be read and serviced when the

bit causing the interrupt is to be rearmed. When ISR_0 is read and the ISADMA bit is cleared, any other low-

to-high transitions in the BUS_STAT register bits that are not masked will still cause an interrupt.

Note 3: If an expected IN token at EP1 (when in isochronous mode) does not arrive, the packet number will be

removed from the TX_FIFO and saved in the TX_COMPLETION_FIFO and a TX_PKT interrupt will be sent

to the MCU. It is the responsibility of the MCU to remove pages assigned to that packet. (Note if the MCU

masks the TX_PKT interrupt, it will not be notified).

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