USB97C102 datasheet(65/80 Pages) SMSC

65 / 80 page

SMSC DS – USB97C102

Page 65

Rev. 03/23/2000

!" Interrupt endpoint for status change reporting

!" Port Power control

!" Frame Timer logic

!" Fault Recovery

!" Selective Suspend and Resume on a port by port basis

!" Selective Reset on a port by port basis

!" The ability to decode the preamble PID and allowing Low Speed port enabling.

!" Full-speed/Low-speed USB transceivers implemented internally; One placed on the upstream port and four

placed on the downstream ports

!" Reflecting Remote Resume to Upstream and enabled down stream USB ports

HUB Block Register Summary

The Register definitions defined below are defined in Table 117 and. These registers are memory mapped into the

8051 MCU memory space defined in Figure 4.

Table 117 - HUB Block Register Summary

ADDRESS

NAME

R/W

DESCRIPTION

PAGE

7FA0

IdVendor-

Low Byte

R/W

Low byte Vendor ID in little endian format (Bit 0

is the LSB)

7FA1

IdVendor-

High Byte

R/W

High byte Vendor ID in little endian format (Bit

0 is the LSB)

7FA2

IdProduct-

Low Byte

R/W

Low byte Product ID value in little endian

format (Bit 0 is the LSB). This value is

initialized by firmware upon initialization/power

up. This value must be initialized prior to the

Hub device participating in and USB

enumeration transactions.

7FA3

IdProduct-

High Byte

R/W

High byte Product ID value in little endian

format (Bit 0 is the LSB). This value is

initialized by firmware upon initialization/power

up. This value must be initialized prior to the

Hub device participating in and USB

enumeration transactions.

7FA4

BcdDevice -

Low Byte

R/W

This 8-bit value defines the USB device release

number, which is assigned by the system

manufacture.

7FA5

BcdDevice -

High Byte

R/W

This 8-bit value defines the USB device release

number, which is assigned by the system

manufacture.

7FA6

HubControl1

R/W

Hub Control register 1

7FA7

Reserved

Reserved – This register should never be

accessed

Table 118 – Hub Control Register1

HubControl1

(0x7FA6- RESET=0x00)

HUB CONTROL REGISTER1

BIT

NAME

R/W

DESCRIPTION

NhubReset

R/W

NHubReset – When this bit is asserted (0), the hub controller is in a reset

state. The hub will not respond to any enumeration or device requests.

When this bit is de-asserted (1), the hub controller is ready to receive

packets from the Root Host Controller. Each Port will then be enabled via

a control packet from the Host

Reserved

R/W

Reserved – This bit should always be cleared (0)

HubBypass5

R/W

When this bit is set(1), Ports 1 and 5 are no longer connected to the hub.

Port 1 (which is connected to the rest of the 97C102) is connected to port

5. Port 5 becomes the upstream of Port 1. See figure on next page. See

Note1.

HubBypass4

R/W

When this bit is set(1), Ports 1 and 4 are no longer connected to the hub.

Port 1 (which is connected to the rest of the 97C102) is connected to port

4. Port 4 becomes the upstream of Port 1. See figure on next page. See

Note1.

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