USB97C102 datasheet(40/80 Pages) SMSC

40 / 80 page

SMSC DS – USB97C102

Page 40

Rev. 03/23/2000

Table 67 – SGDMA Transfer Size Low Register

SGDMA_SIZELOx [x=0..3]

(BASE+5 – RESET = 0x00)

SGDMA_SIZELO

BIT

NAME

R/W

DESCRIPTION

[7:0]

SIZEHIx

[x=0..3]

R/W

Contains the low byte of the payload

data size (in bytes).

Note 1: The SGDMA_SIZEHIx [x=0..3] and SGDMA_SIZELOx [x=0..3] registers are used when the channel [0..3] is

configured for an ISA memory operation or for a MMU operation without a Packet Header.

Note 2: The MCU must not write to these registers unless the channel is disabled (CHANNEL_ENABLED = 0 in

Table 68 – SGDMA Total Packets in Channel Register

SGDMA_TOTAL_PKTSx [x=0..3]

(BASE+6 – RESET = 0x00)

SGDMA_TOTAL_PKTS

BIT

NAME

DESCRIPTION

[7:5]

Reserved

Reserved – Read back as 0

[4:0]

NUMPCKTS

Number of packets currently in the

channel [0..3]

Note 1: This register contains a count of the total number of packets in the corresponding SGDMA channel [0..3]. It

is incremented when the MCU puts a packet number into the SGDMA_START_FIFOx [x=0..3] and is

decremented when the MCU pops a packet from the SGDMA_DONE_FIFOx [x=0..3].

Table 69 – SGDMA Total Packets in the Done FIFO Register

SGDMA_DONE_PCKTSx [x=0..3]

(BASE+7 – RESET = 0x00)

SGDMA_DONE_PCKTS

BIT

NAME

DESCRIPTION

[7:5]

Reserved

Reserved – Read back as 0

[4:0]

NUMPCKTS

Number of packets in the

SGDMA_DONE_FIFOx [x=0..3]

Note 1: This register contains a count of the total number of packets in the SGDMA_DONE_FIFOx [x=0..3]. It is

incremented when the SGDMA puts a packet number into the SGDMA_DONE_FIFOx [x=0..3] and is

decremented when the MCU pops a packet from the SGDMA_DONE_FIFOx [x=0..3].

Table 70 – SGDMA Status Register

SGDMA_STSx [x=0..3]

(BASE+8 – RESET = 0x00)

SGDMA_STS

BIT

NAME

DESCRIPTION

DMA_BUSY

Will be Set (1) while an SGDMA transfer is in progress

ISA_DONE

Will be Set (1) after an ISA memory – ISA device transfer is

completed. Resets to 0 when the channel is disabled

(CHANNEL_ENABLE=0 in register SGDMA_CMDx [x=0..3])

M2M_INCOMPLETE

(Channel 0 only)

Set(1) only when all of the following are true:

Memory-to-Memory transfer

MMU memory is the target

SGDMA_START_FIFO1 is not empty

SGDMA_SIZEHI0 = 0

SGDMA_SIZELO0 = 0

SGDMA Channel 0 is enabled

SGDMA Channel 1 is enabled

Clear(0) when they are not all true

Reserved

Reserved – Read back as 0.

(for Channels 1, 2, and 3)

Reserved

Reserved – Read back as 0.

DONE_FIFO_FULLx

[x=0..3]

Set(1) when SGDMA_DONE_FIFOx [x=0..3] is full

Clear(0) when SGDMA_DONE_FIFOx [x=0..3] is not full

DONE_FIFO_EMPTYx

[x=0..3]

Set(1) when SGDMA_DONE_FIFOx[x=0..3] is empty

Clear(0) when SGDMA_DONE_FIFOx[x=0..3] is not empty

USB97C102 датащи(PDF) 40 Page - SMSC Corporation

USB97C102 датащи(HTML) 40 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

датащи скачать

ссылки URL