USB97C102 datasheet(43/80 Pages) SMSC

43 / 80 page

SMSC DS – USB97C102

Page 43

Rev. 03/23/2000

Table 74 –Low Byte of the PIO ISA Address

PIO_ADLO

(0x7FDA – RESET = 0x00)

PIO_ADLO

BIT

NAME

R/W

DESCRIPTION

[7:0]

PIOADDRLO

R/W

The low byte of the ISA address

Note 1: The MCU must not write these registers until PIO_BUSY=0 in the PIO_CSR register.

Note 2: PIO Read transfers and the first transfer of PIO Read Multiple transfers are initiated by writing to

the PIO_ADLO register.

Table 75 – PIO Data Register

PIO_DATA

(0x7FDB – RESET = 0x00)

PIO_DATA

BIT

NAME

R/W

DESCRIPTION

[7:0]

PIODATA

R/W

The Data for the PIO transfer

Note 1: The MCU must not read this register until PIO_BUSY=0 in the PIO_CSR register.

Note 2: PIO Write transfers are initiated by writing to the PIO_DATA register.

PIO Read Multiple transfers (except for the first transfer) are initiated by reading the PIO_DATA

Table 76 – PIO Command/Status Register

PIO_CSR

(0x7FDC – RESET = 0x00)

PIO_CSR

BIT

NAME

R/W

DESCRIPTION

PIO_BUSY

Will be set(1) when a PIO transfer is in progress

Reserved

R/W

Reserved – Read back as 0

Programs the width of the RD/WR strobes (nIOR, nIOW,

nMEMR, nMEMW)

Strobe Width

Invalid

3 DMACLKs

4 DMACLKs

5 DMACLKs

6 DMACLKs

Invalid

[5:3]

STROBEWIDTH

R/W

For ISA Read accesses, the data must be valid one

DMACLK cycle before the trailing edge of the read strobe.

MEMORY

R/W

Set(1) to indicate an ISA memory transfer.

Clear(0)to indicate an ISA I/O transfer.

Transfer Type

Disable

Write

Read

[1:0]

TRANSFERTYPE

R/W

Read Multiple

Note 1: The STROBEWIDTH and MEMORY bits of the PIO_CSR register must not be changed unless

TRANSFERTYPE=00 (disabled) and PIO_BUSY=0 in the PIO_CSR register.

Note 2: The Ready input can be used to stretch the width of the RD/WR strobes generated by the PIO.

When the READY input is high, the strobes will be as programmed in the PIO_CSR register.

!" PIO Writes: In order to affect the nIOW or nMEMW strobes, the READY signal must go low at least 2

DMACLK periods before the scheduled rising edge of the strobe, and then the strobe will remain low

until 3 DMACLK periods after READY goes high. PIO Reads: In order to affect the nIOR or nMEMW

strobes, the READY signal must go low at least 3 DMACLK periods before the scheduled rising edge of

the strobe, and then the strobe will remain low for 5 DMACLK periods after READY goes high. The read

Data must be valid within 4 DMACLKS after READY goes high so that the Data is available at least 1

DMACLK period before the rising edge of the read strobe.

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