USB97C102 datasheet(44/80 Pages) SMSC

44 / 80 page

SMSC DS – USB97C102

Page 44

Rev. 03/23/2000

MEMORY MANAGEMENT UNIT (MMU) REGISTER DESCRIPTION

MMU Interface Registers

Table 77 - MMU Data Window Register

MMU_DATA

(0x6000)

MMU DATA WINDOW REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:0]

[D7:D0]

R/W

Data Packet Window.

When RCV in the PRH register = '1', this is the byte pointed to by

the packet number on the top of the RXFIFO, and the packet

offset of PRH:PRL.

When RCV in the PRH register = '0', this is the byte pointed to by

the packet number in the PNR register, and the packet offset of

PRH:PRL.

Notes:

The Read FIFO may take at most 1.218µs after the PNH is written to present valid data.

The Write FIFO may take at most 2.520µs after writing the last byte of data to the FIFO to finish writing that data

to the buffer.

The worst case sequential access times to the FIFOs while the 8237 is simultaneously arbitrating for the MMU,

and a USB packet is currently being transferred, is 588ns.

(READ) Therefore, after changing the PRH register, the 8051 should wait at least 2 instruction cycles (at

12MHz) before reading from this register. After waiting, the 8051, in auto-increment mode (PRH bit 6=1),

can read a byte every cycle (at up to 16MHz).

(WRITE) The data register mode can be switched to write at any time, and data can be written immediately

on every instruction cycle. After writing data, the 8051 should wait at least 3 instruction cycles (at 12MHz)

before changing the PNR or PRH :PRL registers for a Read . Again, after waiting 1.218µs, the 8051 can

read a byte every instruction cycle.

Each endpoint will have a three bit up/dn counter which will maintain the number of packets queued for transmit at

that endpoint. These counters are readable through these registers (there are sixteen – from 7F40 to 7F4F).

Table 78 – Tx FIFO Counter

TX_FIFOx

(0x7F40-0x7F4F)

Tx FIFO Counter

BIT

NAME

R/W

DESCRIPTION

[7:3]

Reserved

[2:0]

TxFIFO Count

This field will contain the number of packets that are queued for

transmit at each endpoint. It is incremented when there is a push

on the Tx FIFO of the corresponding endpoint, and it is

decremented when there is a pop on the Tx FIFO of the

corresponding endpoints.

Table 79 - Pointer Register (Low)

PRL

(0x7F50)

POINTER REGISTER (LOW)

BIT

NAME

R/W

DESCRIPTION

[7:0]

A[7:0]

R/W

LSB of the (0-1277 Max) offset of the allocated Packet Pointed to

by PNR. The byte(s) pointed to by this register can be read and

written to by the MCU at 0x6000.

Note 1: This register must be written before PRH .

Note 2: The value read from this register is not necessarily what was last written to it, but actually the last address

used to access the buffer RAM.

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