USB97C102 datasheet(51/80 Pages) SMSC

51 / 80 page

SMSC DS – USB97C102

Page 51

Rev. 03/23/2000

Table 92 - Transmit FIFO Status Register D

TXSTAT_D

(0x7F63 - RESET=0x55)

TRANSMIT FIFO STATUS REGISTER D

BIT

NAME

R/W

DESCRIPTION

EP15TX_EMPTY

Endpoint 15 Transmit Packet FIFO Status

Bits [7:6]='11' Invalid

Bits [7:6]='10' Empty (No Packets queued)

Bits [7:6]='01' Full (5 Packets queued)

Bits [7:6]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP15TX_FULL

EP14TX_EMPTY

Endpoint 14 Transmit Packet FIFO Status

Bits [5:4]='11' Invalid

Bits [5:4]='10' Empty (No Packets queued)

Bits [5:4]='01' Full (5 Packets queued)

Bits [5:4]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP14TX_FULL

EP13TX_EMPTY

Endpoint 13 Transmit Packet FIFO Status

Bits [3:2]='11' Invalid

Bits [3:2]='10' Empty (No Packets queued)

Bits [3:2]='01' Full (5 Packets queued)

Bits [3:2]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP13TX_FULL

EP12TX_EMPTY

Endpoint 12 Transmit Packet FIFO Status

Bits [1:0]='11' Invalid

Bits [1:0]='10' Empty (No Packets queued)

Bits [1:0]='01' Full (5 Packets queued)

Bits [1:0]='00' Partially Full (1, 2, 3, or 4 Packets queued)

EP12TX_FULL

Table 93 - TX Management Register 1

TX_MGMT

(0x7F67 - RESET=0x00)

TX Management Register 1

BIT

NAME

R/W

DESCRIPTION

[7:1]

Reserved

MEM_DALL

R/W

Memory deallocate Mode

0 = Auto

1 = Manual deallocation, but the TX FIFO Pop is still

automatic.

This control bit selects between Auto and Manual memory

pages deallocation. This bit should be statically set at the

start of operation, and can not be changed during or if

about to transmit. This bit defaults to “0” for normal

operation. When set, the MCU handles freeing up the

memory pages.

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