USB97C102 datasheet(42/80 Pages) SMSC

42 / 80 page

SMSC DS – USB97C102

Page 42

Rev. 03/23/2000

Note 2: Memory-to-memory transfer is a special case and is handled as follows. A memory-to-memory

transfer supports transfers only between MMU memory and ISA memory, in either direction. The

source must be Channel 0, the destination must be Channel 1.

!" MMU memory to ISA memory transfers

Initially, the MCU performs the following:

Clears the SGDMA_SIZEHI0/LO0 registers.

Sets the SGDMA_ADHI1/LO1 registers to the ISA Address.

After each TC, the SGDMA will add the size of the completed transfer to the SGDMA_ADHI1/LO1 registers.

If PKT_HDR=1 in the SGDMA_CMD0 register, the transfer size comes from the MMU packet header. If

PKT_HDR=0 in the SGDMA_CMD0 register, the transfer size is the value in SGDMA_SIZEHI1/LO1 registers.

!" ISA memory to MMU memory transfers

Initially, the MCU performs the following:

Sets the SGDMA_ADHI0/LO0 to the ISA Address.

Sets the SGDMA_SIZEHI0/LO0 to the ISA buffer size.

Sets the SGDMA_SIZEHI1/LO1 to the session transfer size.

After each TC, the SGDMA will add the session transfer size to the SGDMA_ADHI0/LO0 registers and subtract

the session transfer size from the SGDMA_SIZEHI0/LO0 registers.

The actual transfer size is the lesser of the values in the SGDMA_SIZEHI1/ LO1 and the SGDMA_SIZEHI0/LO0

registers.

If PKT_HDR=1 in register SGDMA_CMD1, then the actual transfer size plus 8 will be written to the packet

memory at an offset of 6.

When the SGDMA_SIZEHI0/LO0 registers reach a value of 0, the ISA buffer has been completely transferred. If

the SGDMA_START_FIFO1 is not yet empty when the ISA buffer has been completely transferred, the

M2M_INCOMPLETE bit in the SGDMA_STS0 register will be set.

!" During a memory-to-memory transfer, if either Channel 0 or Channel 1 is Disabled during the SGDMA cycle,

then the packet number for the MMU channel is put into the SGDMA_DONE_FIFOxx [0 or 1]. However, none of

the updates to the address or size registers occur, and the SGDMA returns to idle and is ready for another cycle.

!" For memory-to-memory transfers, the SGDMA_ADHI0, SGDMA_ADLO0, SGDMA_ADHI1, SGDMA_ADLO1,

SGDMA_SIZEHI0, and SGDMA_SIZELO0 must not be read by the MCU until both channels 0 and 1 are not

Busy (DMA_BUSY=0 in SGDMA_STS0 and SGDMA_STS1).

PIO REGISTER DESCRIPTION

Table 72 – Upper Byte of the PIO ISA Address

PIO_ADHI

(0x7FD8 – RESET = 0x00)

PIO_ADHI

BIT

NAME

R/W

DESCRIPTION

[7:4]

Reserved

R/W

Reserved – Read back as 0

[3:0]

PIOADDRHI

R/W

The upper 4 bits of the ISA address

Table 73 –Middle Byte of the PIO ISA Address

PIO_ADMID

(0x7FD9 – RESET = 0x00)

PIO_ADMID

BIT

NAME

R/W

DESCRIPTION

[7:0]

PIOADDRMID

R/W

The middle byte of the ISA address

USB97C102 датащи(PDF) 42 Page - SMSC Corporation

USB97C102 датащи(HTML) 42 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

датащи скачать

ссылки URL