USB97C102 datasheet(36/80 Pages) SMSC

36 / 80 page

SMSC DS – USB97C102

Page 36

Rev. 03/23/2000

CH_CMD

(ISA 0x0008)

COMMAND REGISTER

BIT

NAME

R/W

DESCRIPTION

ADDR_HOLD

Channel 0 Address Hold

0 = Disable

1 = Hold Enable

MEM2MEM

Memory-to-Memory

0 = Disable

1 = Enable

Table 54 - 8237 Write Single Request Register

CH_REQ

(ISA 0x0009)

WRITE REQUEST REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:3]

Reserved

SET_CLR

Force Internal DMA Request Bit

0 = Clear

1 = Set

[1:0]

SEL[1:0]

'00' = Select Channel 0 DREQ

'01' = Select Channel 1 DREQ

'10' = Select Channel 2 DREQ

'11' = Select Channel 3 DREQ

Table 55 - 8237 Write Single Mask Register

CH_MASK

(ISA 0x000A)

WRITE SINGLE MASK REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:3]

Reserved

SET_CLR

Set Channel Mask Bit

0 = Clear

1 = Set

[1:0]

SEL[1:0]

'00' = Select Channel 0 Mask Bit

'01' = Select Channel 1 Mask Bit

'10' = Select Channel 2 Mask Bit

'11' = Select Channel 3 Mask Bit

Table 56 - Write Mode Register

DMA_MODE

(ISA 0x000B)

WRITE MODE REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:6]

MODE[1:0]

'00' = Demand Mode Select

'01' = Single Mode Select

'10' = Block Mode Select

'11' = Cascade Mode Select

INC_DEC

Auto-increment/Decrement

0 = Increment

1 = Decrement

AUTO_INIT

Auto-initialization

0 = Disable

1 = Enable

[3:2]

R/WV[1:0]

'00' = Verify Transfer

'01' = Write Transfer

'10' = Read Transfer

'11' = Illegal

'XX' if bits 6 and 7 = '11' Or if CH_CMD register bit 0

= 1 (memory-to-memory transfer)

[1:0]

SEL[1:0]

'00' = Select Channel 0

'01' = Select Channel 1

'10' = Select Channel 2

'11' = Select Channel 3

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