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BLUENRG-2 датащи(PDF) 113 Page - STMicroelectronics

номер детали BLUENRG-2
подробное описание детали  Bluetooth® low energy wireless system-on-chip
PDF  190 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

BLUENRG-2 датащи(HTML) 113 Page - STMicroelectronics

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BlueNRG-2
Functional details
DocID030675 Rev 2
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Table 128: FLASH
– TIMETRIM2 register description: address offset
FLASH_BASE_ADDR+0x2C
Bit
Field name
Reset
RW
Description
31:0
TIMETRIM2
0x0B156506
RW
Trimming values for flash erase/modify sequences.
Table 129: FLASH
– TIMETRIM3 register description: address offset
FLASH_BASE_ADDR+0x30
Bit
Field name
Reset
RW
Description
31:0
TIMETRIM3
0x00000011
RW
Trimming values for flash wake-up sequence.
Table 130: FLASH
– DATA0 register description: address offset FLASH_BASE_ADDR+0x40
Bit
Field name
Reset
RW
Description
31:0
DATA0
0xFFFFFFFF
RW
Program cycle data.
Table 131: FLASH
– DATA1 register description: address offset FLASH_BASE_ADDR+0x44
Bit
Field name
Reset
RW
Description
31:0
DATA1
0xFFFFFFFF
RW
Program cycle data.
Table 132: FLASH
– DATA2 register description: address offset FLASH_BASE_ADDR+0x48
Bit
Field name
Reset
RW
Description
31:0
DATA2
0xFFFFFFFF
RW
Program cycle data.
Table 133: FLASH
– DATA3 register description: address offset FLASH_BASE_ADDR+0x4C
Bit
Field name
Reset
RW
Description
31:0
DATA3
0xFFFFFFFF
RW
Program cycle data.
3.12
GPIO
3.12.1
Introduction
The BlueNRG-2 offers 14 GPIOs (WCSP34 package), 15 GPIOs (QFN32 package) or 26
GPIOs (QFN48 package).
The programmable I/O pin can be configured for operating as:
Programmable GPIOs
Peripheral input or output line of standard communication interfaces
PDM processor data/clock
2 PWM sources (PWM0 and PWM1 independently configurable) and 4 PWM output
pins (IO2, IO3, IO4 and IO5).
5 wakeup sources from standby and sleep mode
Each I/O can generate an interrupt independently to the selected mode. Interrupts are
generated depending on a level or edge



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