PCI1221 datasheet(97/123 Pages) TI

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ExCA memory window 0–4 end-address high-byte register (index 13h, 1Bh, 23h, 2Bh, 33h)

Bit

Name

ExCA memory window 0–4 end-address high byte

Type

R/W

Default

ExCA memory window 0 end-address high byte

Offset:

CardBus socket address + 813h; Card A ExCA offset 13h

Card B ExCA offset 53h

ExCA memory window 1 end-address high byte

Offset:

CardBus socket address + 81Bh; Card A ExCA offset 1Bh

Card B ExCA offset 5Bh

ExCA memory window 2 end-address high byte

Offset:

CardBus socket address + 823h; Card A ExCA offset 23h

Card B ExCA offset 63h

ExCA memory window 3 end-address high byte

Offset:

CardBus socket address + 82Bh; Card A ExCA offset 2Bh

Card B ExCA offset 6Bh

ExCA memory window 4 end-address high byte

Offset:

CardBus socket address + 833h; Card A ExCA offset 33h

Card B ExCA offset 73h

Type:

Read only, read/write (see individual bit descriptions)

Default:

00h

Size:

One byte

Description: These registers contain the high nibble of the 16-bit memory window end address for memory

windows 0, 1, 2, 3, and 4. The lower four bits of these registers correspond to bits A23-A20 of

the end address. In addition, the memory window wait states are set in this register. See

Table 48 for a complete description of the register contents.

Table 48. ExCA Memory Window 0–4 End-Address High-Byte Register (Index 13h, 1Bh, 23h, 2Bh, 33h)

BIT

SIGNAL

TYPE

FUNCTION

7-6

MEMWS

R/W

Wait state. Bits 7-6 specify the number of equivalent ISA wait states to be added to 16-bit memory accesses.

The number of wait states added is equal to the binary value of these two bits.

5-4

RSVD

Reserved. Bits 5-4 are read only and return 0s when read. Write transactions have no effect.

3-0

ENDHN

R/W

End-address high nibble. Bits 3-0 represent the upper address bits A23–A20 of the memory window end

address.

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