PCI1221 datasheet(79/123 Pages) TI

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serial bus control and status register

Bit

Name

Serial bus control and status

Type

R/W

R/C

R/W

R/C

Default

Serial bus control and status

Type:

Read only, read/write, read/clear (see individual bit descriptions)

Offset:

B3h (function 0)

Default:

00h

Description: The serial bus control and status register is used to communicate serial bus status information

and select the quick command protocol. The REQBUSY bit in this register must be polled

during serial bus byte reads to indicate when data is valid in the serial bus data register. See

Table 37 for a complete description of the register contents.

Table 37. Serial Bus Control and Status Register

BIT

SIGNAL

TYPE

FUNCTION

PROT_SEL

R/W

Protocol select. When bit 7 is set, the send byte protocol is used on write requests and the receive byte

protocol is used on read commands. The word address byte in the serial bus index register is not output

by the PCI1221 when bit 7 is set.

RSVD

Reserved. Bit 6 is read only and returns zero when read.

REQBUSY

Requested serial bus access busy. Bit 5 indicates that a requested serial bus access (byte read or write)

is in progress. A request is made, and bit 5 is set, by writing to the serial bus slave address register. Bit

5 must be polled on reads from the serial interface. After the byte read access has been requested, the

read data is valid in the serial bus data register.

ROMBUSY

Serial EEPROM Busy status. Bit 4 indicates the status of the PCI1221 serial EEPROM circuitry. Bit 4 is

set during the loading of the subsystem ID and other default values from the serial bus EEPROM.

0 = Serial EEPROM circuitry is not busy

1 = Serial EEPROM circuitry is busy

SBDETECT

R/C

Serial bus detect. When bit 3 is set, it indicates that the serial bus interface is detected. A pulldown resistor

must be implemented on the LATCH terminal for bit 3 to be set. If bit 3 is reset, then the MFUNC4 and

MFUNC1 terminals can be used for alternate functions such as general-purpose inputs and outputs.

0 = Serial bus interface not detected

1 = Serial bus interface detected

SBTEST

R/W

Serial bus test. When bit 2 is set, the serial bus clock frequency is increased for test purposes.

0 = Serial bus clock at normal operating frequency,

100 kHz (default)

1 = Serial bus clock frequency increased for test purposes

REQ_ERR

R/C

Requested serial bus access error. Bit 1 indicates when a data error occurs on the serial interface during

a requested cycle and may be set due to a missing acknowledge. Bit 1 is cleared by a write back of 1.

0 = No error detected during user requested byte read or write cycle

1 = Data error detected during user requested byte read or write cycle

ROM_ERR

R/C

EEPROM data error status. Bit 0 indicates when a data error occurs on the serial interface during the

auto-load from the serial bus EEPROM and may be set due to a missing acknowledge. Bit 0 is also set

on invalid EEPROM data formats. Refer to

serial bus interface implementation on page 29 for details on

EEPROM data format. Bit 0 is cleared by a write back of 1.

0 = No error detected during auto-load from serial bus EEPROM

1 = Data error detected during auto-load from serial bus EEPROM

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