PCI1221 datasheet(19/123 Pages) TI

19 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

CardBus PC Card interface system (slots A and B)

TERMINAL

PIN NUMBER

I/O

FUNCTION

NAME

SLOT A†

SLOT B‡

TYPE

FUNCTION

PDV

GHK

PDV

GHK

CCLK

112

P18

CardBus PC Card clock. CCLK provides synchronous timing for all transactions on

the CardBus interface. All signals except CRST, CCLKRUN, CINT, CSTSCHG,

CAUDIO, CCD2-1, and CVS2-CVS1 are sampled on the rising edge of CCLK, and

all timing parameters are defined with the rising edge of this signal. CCLK operates

at the PCI bus clock frequency, but it can be stopped in the low state or slowed down

for power savings.

CCLKRUN

139

H18

CardBus PC Card clock run. CCLKRUN is used by a CardBus PC Card to request

an increase in the CCLK frequency, and by the PCI1221 to indicate that the CCLK

frequency is going to be decreased.

CRST

124

L18

I/O

CardBus PC Card reset. CRST is used to bring CardBus PC Card-specific

registers, sequencers, and signals to a known state. When CRST is asserted, all

CardBus PC Card signals must be 3-stated, and the PCI1221 drives these signals

to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must

be synchronous to CCLK.

† Terminal name for slot A is preceded with A_. For example, the full name for terminals 112 and P18 are A_CCLK.

‡ Terminal name for slot B is preceded with B_. For example, the full name for terminals 48 and P6 are B_CCLK.

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