PCI1221 datasheet(30/123 Pages) TI

30 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

serial bus interface protocol (continued)

All data transfers are initiated by the serial bus master. The beginning of a data transfer is indicated by a start

condition, which is signalled when the SDA line transitions to low state while SCL is in the high state, as

illustrated in Figure 9. The end of a requested data transfer is indicated by a stop condition, which is signalled

by a low to high transition of SDA while SCL is in the high state, as shown in Figure 9. Data on SDA must remain

stable during the high state of the SCL signal, as changes on the SDA signal during the high state of SCL are

interpreted as control signals, that is, a start or a stop condition.

SDA

SCL

Start

Condition

Stop

Condition

Change of

Data Allowed

Data Line Stable,

Data Valid

Figure 9. Serial Bus Start/Stop Conditions and Bit Transfers

Data is transferred serially in 8-bit bytes. The number of bytes that may be transmitted during a data transfer

is unlimited, however, each byte must be completed with an acknowledge bit. An acknowledge (ACK) is

indicated by the receiver pulling the SDA signal low so that it remains low during the high state of the SCL signal.

The acknowledge protocol is illustrated in Figure 10.

SCL From

Master

SDA Output

By Transmitter

SDA Output

By Receiver

Figure 10. Serial Bus Protocol Acknowledge

The PCI1221 is a serial bus master; all other devices connected to the serial bus external to the PCI1221 are

slave devices. As the bus master, the PCI1221 drives the SCL clock at nearly 100 kHz during bus cycles and

three-states SCL (zero frequency) during idle states.

Typically, the PCI1221 masters byte reads and byte writes under software control. Doubleword reads are

performed by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under

software control. Refer to

serial bus EEPROM application on page 32 for details on how the PCI1221

automatically loads the subsystem identification and other register defaults through a serial bus EEPROM.

A byte write is illustrated in Figure 11. The PCI1221 issues a start condition and sends the seven bit slave device

address and the command bit zero. A zero in the R/W command bit indicates that the data transfer is a write.

The slave device acknowledges if it recognizes the address. If there is no acknowledgment received by the

PCI1221, then an appropriate status bit is set in the serial bus control and status register. The word address

byte is then sent by the PCI1221 and another slave acknowledgment is expected. Then the PCI1221 delivers

the data byte MSB first and expects a final acknowledgment before issuing the stop condition.

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