PCI1221 datasheet(43/123 Pages) TI

43 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PCI power management (PCIPM) (continued)

The OS identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of new

capabilities is indicated by a 1 in the capabilities list (CAPLIST) bit in the status register (bit 4) and providing

access to a capabilities list.

The capabilities pointer provides access to the first item in the linked list of capabilities. For the PCI1221, a

CardBus bridge with PCI configuration space header type 2, the capabilities pointer is mapped to an offset

of 14h. The first byte of each capability register block is required to be a unique ID of that capability. PCI power

management has been assigned an ID of 01h. The next byte is a pointer to the next pointer item in the list of

capabilities. If there are no more items in the list, the next item pointer should be set to 0. The registers following

the next item pointer are specific to the function’s capability. The PCIPM capability implements the register block

outlined in Table 14.

Table 14. Power-Management Registers

OFFSET

Power-management capabilities

Next item pointer

Capability ID

Data

PMCSR bridge support extensions

Power-management control status (CSR)

The power management capabilities register is a static read-only register that provides information on the

capabilities of the function related to power management. The PMCSR register enables control of

power-management states and enables/monitors power-management events. The data register is an optional

For more information on PCI power management refer to the

PCI Bus Power Management Interface

Specification.

ACPI support

The ACPI specification provides a mechanism that allows unique pieces of hardware to be described to the

ACPI driver. The PCI1221 offers a generic interface that is compliant with ACPI design rules.

Two doublewords of general purpose ACPI programming bits reside in PCI1221 PCI configuration space at

offset A8h. The programming model is broken into status and control functions. In compliance with ACPI, the

top level event status and enable bits reside in GPE_STS and GPE_EN registers. The status and enable bits

are implemented as defined by ACPI, and illustrated in Figure 20.

Status Bit

Event Output

Event Input

Enable Bit

Figure 20. Block Diagram of a Status/Enable Cell

The status and enable bits are used to generate an event that allows the ACPI driver to call a control method

associated with the pending status bit. The control method can then control the hardware by manipulating the

hardware control bits or by investigating child status bits and calling their respective control methods. A

hierarchical implementation would be somewhat limiting, however, as upstream devices would have to remain

in some level of power state to report events.

For more information of ACPI refer to the

Advanced Configuration and Power Interface Specification.

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