PCI1221 datasheet(67/123 Pages) TI

67 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

device control register

Bit

Name

Device control

Type

R/W

Default

Device control

Type:

Read only, read/write (see individual bit descriptions)

Offset:

92h (functions 0, 1)

Default:

66h

Description: The device control register is provided for PCI1130 compatibility and contains bits that are

shared between functions 0 and 1. The interrupt mode select is programmed through this

programmed through this register. See Table 25 for a complete description of the register

contents.

Table 25. Device Control Register

BIT

SIGNAL

TYPE

FUNCTION

RSVD

Reserved. Bit 7 Returns 0 when read.

6†

3VCAPABLE

R/W

3-V socket capable force

0 = Not 3-V capable

1 = 3-V capable (default)

IO16R2

R/W

Diagnostic bit. This bit defaults to 1.

RSVD

Reserved. Bit 4 returns 0 when read. Write transactions have no effect.

3†

TEST

R/W

TI test. Only a 0 should be written to bit 3.

2–1

INTMODE

R/W

Interrupt mode. Bit 2–1 select the interrupt signaling mode. The interrupt mode bits are encoded:

00 = Parallel PCI interrupts only

01 = Parallel IRQ and parallel PCI interrupts

10 = IRQ serialized interrupts and parallel PCI interrupt

11 = IRQ and PCI serialized interrupts (default)

0†

RSVD

R/W

Reserved. This read/write bit is reserved for test purposes. O

nly 0 should be written to this bit.

† These bits are global and should be accessed only through function 0.

PCI1221 датащи(PDF) 67 Page - Texas Instruments

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