PCI1221 datasheet(23/123 Pages) TI

23 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

peripheral component interconnect (PCI) interface

The PCI1221 is fully compliant with the PCI Local Bus Specification Rev. 2.2. The PCI1221 provides all required

signals for PCI master or slave operation, and may operate in either a 5-V of 3.3-V signaling environment by

connecting the VCCP terminals to the desired voltage level. In addition to the mandatory PCI signals, the

PCI1221 provides the optional interrupt signals INTA and INTB.

PCI bus lock (LOCK)

The bus-locking protocol defined in the PCI specification is not highly recommended, but is provided on the

PCI1221 as an additional compatibility feature. The PCI LOCK signal can be routed to the MFUNC4 terminal

via the multifunction routing register, see the

multifunction routing register description on page 62 for details.

Note that the use of LOCK is only supported by PCI-to-CardBus bridges in the downstream direction (away from

the processor).

PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is

asserted, nonexclusive transactions can proceed to an address that is not currently locked. A grant to start a

transaction on the PCI bus does not guarantee control of LOCK; control of LOCK is obtained under its own

protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of LOCK.

Note that the CardBus signal for this protocol is CBLOCK to avoid confusion with the bus clock.

An agent may need to do an exclusive operation because a critical access to memory might be broken into

several transactions, but the master wants exclusive rights to a region of memory. The granularity of the lock

is defined by PCI to be 16 bytes, aligned. The lock protocol defined by PCI allows a resource lock without

interfering with nonexclusive real-time data transfer, such as video.

The PCI bus arbiter may be designed to support only complete bus locks using the LOCK protocol. In this

scenario, the arbiter will not grant the bus to any other agent (other than the LOCK master) while LOCK is

asserted. A complete bus lock may have a significant impact on the performance of the video. The arbiter that

supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified

line when a locked operation is in progress.

The PCI1221 supports all LOCK protocol associated with PCI-to-PCI bridges, as also defined for

PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which can

solve a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can occur

if a CardBus target supports delayed transactions and blocks access to the target until it completes a delayed

read. This target characteristic is prohibited by the 2.2 PCI specification, and the issue is resolved by the PCI

master using LOCK.

loading subsystem identification

The subsystem vendor ID register and subsystem ID register make up a doubleword of PCI configuration space

located at offset 40h for functions 0 and 1. This doubleword register is used for system and option card (mobile

dock) identification purposes and is required by some operating systems. Implementation of this unique

identifier register is a PC 95 requirement.

The PCI1221 offers two mechanisms to load a read-only value into the subsystem registers. The first

mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the

subsystem registers is read only, but can be made read/write by setting the SUBSYSRW bit in the system control

the registers at offset 40h. The BIOS must clear the SUBSYSRW bit such that the subsystem vendor ID register

and subsystem ID register is limited to read-only access. This approach saves the added cost of implementing

the serial electrically erasable programmable ROM (EEPROM).

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