PCI1221 datasheet(73/123 Pages) TI

73 / 123 page

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

general-purpose event status register

Bit

Name

Power-management control/status

Type

R/C

Default

General-purpose event status

Type:

Read only, read/clear (see individual bit descriptions)

Offset:

A8h (function 0)

Default:

0000h

Description: The general-purpose event status register contains status bits that are set when events occur

that are controlled by the general-purpose control register. The bits in this register and the

corresponding GPE are cleared by writing a 1 to the corresponding bit location. The status bits

in this register do not depend upon the state of a corresponding bit in the general-purpose

enable register. Access this register only through function 0. See Table 30 for a complete

description of the register contents.

Table 30. General-Purpose Event Status Register

BIT

SIGNAL

TYPE

FUNCTION

ZV0_STS

R/C

PC card socket 0 ZV Status. Bit 15 is set on a change in status of the ZVENABLE bit in the

function 0 PC card controller function of the PCI1221.

ZV1_STS

R/C

PC card socket 1 ZV Status. Bit 14 is set on a change in status of the ZVENABLE bit in the

function 1 PC card controller function of the PCI1221.

13–12

RSVD

Reserved. These bits are read only and return zero when read.

PWR_STS

R/C

Power change status. Bit 11 is set when software has changed the power state of either socket.

A change in either VCC or VPP for either socket causes this bit to be set.

10–9

RSVD

Reserved. These bits are read only and return zero when read.

VPP12_STS

R/C

12 Volt VPP request status. Bit 8 is set when software has changed the requested Vpp level to

or from 12 Volts for either of the two PC Card sockets.

7–5

RSVD

Reserved. These bits are read only and return zero when read.

GP4_STS

R/C

GPI4 Status. Bit 4 is set on a change in status of the MFUNC5 terminal input level.

GP3_STS

R/C

GPI3 Status. Bit 3 is set on a change in status of the MFUNC4 terminal input level .

GP2_STS

R/C

GPI2 Status. Bit 2 is set on a change in status of the MFUNC2 terminal input level.

GP1_STS

R/C

GPI1 Status. Bit 1 is set on a change in status of the MFUNC1 terminal input level.

GP0_STS

R/C

GPI0 Status. Bit 0 is set on a change in status of the MFUNC0 terminal input level.

PCI1221 датащи(PDF) 73 Page - Texas Instruments

PCI1221 датащи(HTML) 73 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL