PCI1221 datasheet(33/123 Pages) TI

33 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

serial bus EEPROM application (continued)

Note, the eight-byte data structure is important to provide correct addressing per the doubleword read format

shown in Figure 13. In addition, the reference offsets must be loaded in the EEPROM in sequential order, that

is 01h, 02h, 03h, 04h. If the offsets are not sequential, the registers may be loaded incorrectly.

serial bus power switch application

The PCI1221 does not automatically control a serial bus power switch transparently to host software as it does

for P2C power switches. But, the PCI1221 serial bus interface can be used in conjunction with the power status,

GPE, output, and support software to control a serial bus power switch. If a serial bus power switch interface

is implemented, a pulldown resistor must be provided on the PCI1221 CLOCK terminal to reduce power

consumption.

The PCI1221 supports two common SMBus data write protocols, write byte and send byte formats. The write

byte protocol using a word address of 00h is discussed in

serial bus interface protocol on page 29. The send

byte protocol is shown in Figure 15 using a slave address ‘101001x’. The PROT_SEL bit in the serial bus control

and status register, see Table 37 on page 79, allows the serial bus interface to operate with the send byte

protocol. For more information on programming the serial bus interface, refer to

accessing serial bus devices

through software.

b7 b6 b5 b4 b3

b2 b1 b0

Slave Address

Command Code

R/W

S/P = Start/stop condition

A = Slave acknowledgement

Figure 15. Send Byte Protocol

The power switch may support an interrupt mode to indicate over current or other power switch related events.

The PCI1221 does not implement logic to respond to these events, but does implement a flexible general

purpose interface to control these events through ACPI and other handlers. Refer to

Advanced Configuration

and Power Interface Specification for details on implementing the PCI1221 in an ACPI system.

accessing serial bus devices through software

The PCI1221 provides a programming mechanism to control serial bus devices through software. The

programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 9 lists the

registers used to program a serial bus device through software.

Table 9. PCI1221 Registers Used to Program Serial Bus Devices

PCI OFFSET

DESCRIPTION

B0H

Serial bus data

Contains the data byte to send on write commands or the received data byte on read

commands.

B1H

Serial bus index

The content of this register is sent as the word address on byte writes or reads. This

B2H

Serial bus slave

address

Write transactions to this register initiate a serial bus transaction. The slave device address

and the R/W command selector are programmed through this register.

B3H

Serial bus control

and status

Read data valid, general busy, and general error status are communicated through this

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