PCI1221 datasheet(17/123 Pages) TI

17 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

16-bit PC Card interface control (slots A and B)

TERMINAL

PIN NUMBER

I/O

FUNCTION

NAME

SLOT A†

SLOT B‡

TYPE

FUNCTION

PDV

GHK

PDV

GHK

BVD1

(STSCHG/RI)

138

H19

Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that

include batteries. BVD1 is used with BVD2 as an indication of the condition of the

batteries on a memory PC Card. Both BVD1 and BVD2 are kept high when the

battery is good. When BVD2 is low and BVD1 is high, the battery is weak and

should be replaced. When BVD1 is low, the battery is no longer serviceable and

the data in the memory PC Card is lost. See

ExCA card status-change interrupt

configuration register on page 89 for enable bits. See ExCA card status-change

status bits for this signal.

Status change. STSCHG is used to alert the system to a change in the READY,

write protect, or battery voltage dead condition of a 16-bit I/O PC Card.

Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection.

BVD2

(SPKR)

137

J15

Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that

include batteries. BVD2 is used with BVD1 as an indication of the condition of the

batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery

is good. When BVD2 is low and BVD1 is high, the battery is weak and should be

replaced. When BVD1 is low, the battery is no longer serviceable and the data

in the memory PC Card is lost. See

ExCA card status-change interrupt

configuration register on page 89 for enable bits. See ExCA card status-change

status bits for this signal.

Speaker. SPKR is an optional binary audio signal available only when the card

and socket have been configured for the 16-bit I/O interface. The audio signals

from cards A and B are combined by the PCI1221 and are output on SPKROUT.

CD1

CD2

140

V11

H17

PC Card detect 1 and PC Card detect 2. CD1 and CD2 are internally connected

to ground on the PC Card. When a PC Card is inserted into a socket, CD1 and

CD2 are pulled low. For signal status, see

interface status register on page 88.

CE1

CE2

P13

R13

Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered

address bytes. CE1 enables even-numbered address bytes, and CE2 enables

odd-numbered address bytes.

INPACK

127

L14

Input acknowledge. INPACK is asserted by the PC Card when it can respond to

an I/O read cycle at the current address.

IORD

W15

I/O read. IORD is asserted by the PCI1221 to enable 16-bit I/O PC Card data

output during host I/O read cycles.

IOWR

101

V15

I/O write. IOWR is driven low by the PCI1221 to strobe write data into 16-bit I/O

PC Cards during host I/O write cycles.

U14

Output enable. OE is driven low by the PCI1221 to enable 16-bit memory PC

Card data output during host memory read cycles.

† Terminal name for slot A is preceded with A_. For example, the full name for terminals 127 and L14 are A_INPACK.

‡ Terminal name for slot B is preceded with B_. For example, the full name for terminals 61 and R7 are B_INPACK.

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