PCI1221 datasheet(38/123 Pages) TI

38 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

using parallel PCI interrupts (continued)

Table 12. Interrupt Pin Register Cross Reference

INTERRUPT SIGNALING MODE

INTRTIE

BIT

INTPIN

FUNCTION 0

INTPIN

FUNCTION 1

Parallel PCI interrupts only

0x01 (INTA)

0x02 (INTB)

Parallel IRQ and parallel PCI interrupts

0x01 (INTA)

0x02 (INTB)

IRQ serialized (IRQSER) and parallel PCI interrupts

0x01 (INTA)

0x02 (INTB)

IRQ and PCI serialized (IRQSER) interrupts (default)

0x01 (INTA)

0x02 (INTB)

Parallel PCI interrupts only

0x01 (INTA)

Parallel IRQ and parallel PCI interrupts

0x01 (INTA)

IRQ serialized (IRQSER) and parallel PCI interrupts†

0x01 (INTA)

IRQ and PCI serialized (IRQSER) interrupts†

0x01 (INTA)

† When configuring the PCI1221 functions to share PCI interrupts, multifunction terminal MFUNC3 must

be configured as IRQSER prior to setting the INTRTIE bit.

using serialized IRQSER interrupts

The serialized interrupt protocol implemented in the PCI1221 uses a single terminal to communicate all interrupt

status information to the host controller. The protocol defines a serial packet consisting of a start cycle, multiple

interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The packet

data describes sixteen parallel ISA IRQ signals and the optional four PCI interrupts INTA, INTB, INTC, and

INTD. For details on the IRQSER protocol refer to the document

Serialized IRQ Support for PCI Systems.

SMI support in the PCI1221

The PCI1221 provides a mechanism for interrupting the system when power changes have been made to the

PC Card socket interfaces. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI)

scheme. SMI interrupts are generated by the PCI1221, when enabled, after a write cycle to either the socket

control register of the CardBus register set or the power control register of the ExCA register set causes a power

cycle change sequence sent on the power switch interface.

The SMI control is programmed through 3 bits in the system control register. These bits are SMIROUTE,

SMISTATUS, and SMIENB. The SMI control bits function as described in Table 13.

Table 13. SMI Control

BIT NAME

FUNCTION

SMIROUTE

This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2.

SMISTAT

This socket dependent bit is set when an SMI interrupt is pending. This status flag is cleared by writing back a 1.

SMIENB

When set, SMI interrupt generation is enabled. This bit is shared by functions 0 and 1.

If CSC SMI interrupts are selected, then the SMI interrupt is sent as the CSC on a per socket basis. The CSC

interrupt can be either level or edge mode, depending upon the CSCMODE bit in the ExCA global control

If IRQ2 is selected by SMIROUTE, the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ/Data

slot. In a parallel ISA IRQ system, the support for an active low IRQ2 is provided only if IRQ2 is routed to either

MFUNC3 or MFUNC6 through the multifunction routing register.

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