PCI1221 datasheet(71/123 Pages) TI

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power-management control/status register

Bit

Name

Power-management control/status

Type

R/C

R/W

Default

Power-management control/status

Type:

Read only, read/write, read/clear (see individual bit descriptions)

Offset:

A4h (functions 0, 1)

Default:

0000h

Description: The power-management control/status register determines and changes the current power

state of the PCI1221 CardBus function. The contents of this register are not affected by the

internally-generated reset caused by the transition from D3hot to D0 state. See Table 28 for a

complete description of the register contents.

Table 28. Power-Management Control/Status Register

BIT

SIGNAL

TYPE

FUNCTION

PMESTAT

R/C

PME status. Bit 15 is set when the CardBus function would normally assert PME, independent

of the state of the PME_EN bit. Bit 15 is cleared by a write back of 1, and this also clears the

PME signal if PME was asserted by this function. Writing a 0 to this bit has no effect.

14–13

DATASCALE

Data scale. This 2-bit field is read only, returning 0s when read. The CardBus function does not

return any dynamic data as indicated by the DYN_DATA bit.

12–9

DATASEL

Data select. This 4-bit field is read only and returns 0s when read. The CardBus function does

not return any dynamic data as indicated by the DYN_DATA bit.

R/W

PME enable. Bit 8 enables the function to assert PME. If this bit is cleared, assertion of PME

is disabled.

7–2

RSVD

Reserved. Bits 7–2 are read only and return 0s when read.

1–0

PWR_STATE

R/W

Power state. This 2-bit field is used both to determine the current power state of a function, and

to set the function into a new power state. This field is encoded as:

00 = D0

01 = D1

10 = D2

11 = D3hot

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