PCI1221 datasheet(31/123 Pages) TI

31 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

serial bus interface protocol (continued)

Sb6

b3 b2 b1 b0

b7 b6 b5 b4 b3

b2 b1 b0

Slave Address

Word Address

R/W

S/P = Start/stop condition

A = Slave acknowledgement

b7 b6

b3 b2 b1 b0

Data Byte

Figure 11. Serial Bus Protocol – Byte Write

A byte read is llustrated in Figure 12. The read protocol is very similar to the write protocol except the R/W

command bit must be set to one to indicate a read-data transfer. In addition, the PCI1221 master must

acknowledge reception of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal

during read data transfers. The SCL signal remains driven by the PCI1221 master.

Sb6

b3 b2 b1 b0

b7 b6 b5 b4 b3

b2 b1 b0

Slave Address

Word Address

R/W

S/P = Start/stop condition

A = Slave acknowledgement

b7 b6

b3 b2 b1 b0

Data Byte

Figure 12. Serial Bus Protocol – Byte Read

Figure 13 illustrates EEPROM interface doubleword data collection protocol.

b7 b6 b5 b4 b3

b2 b1 b0

Slave Address

Word Address

R/W

Data Byte 2

Data Byte 1

Data Byte 0

M = Master acknowledgement

S/P = Start/stop condition

A = Slave acknowledgement

Data Byte 3

001

Restart

R/W

Slave Address

Start

Figure 13. EEPROM Interface doubleword Data Collection

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