PCI1221 datasheet(32/123 Pages) TI

32 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

serial bus EEPROM application

When the PCI bus is reset and the serial bus interface is detected, the PCI1221 attempts to read the subsystem

identification and other register defaults from a serial EEPROM. The registers and corresponding bits that may

be loaded with defaults through the EEPROM are provided in Table 8.

Table 8. Registers and Bits Loadable Through Serial EEPROM

PCI OFFSET

OFFSET

REFERENCE

BITS LOADED FROM EEPROM

40h

01h

Subsystem identification

31–0

80h

02h

System control register

31–29, 27, 26, 24, 15, 14, 6–3, 1

8Ch

03h

Multifunction routing register

27–0

90h

04h

Retry status, Card control, device control, diagnostic

31, 28–24, 22, 19–16, 15, 13, 7, 6

The EEPROM data format is detailed in Figure 14. This format must be followed for the PCI1221 to properly

load initializations from a serial EEPROM. Any undefined condition results in a terminated load and sets the

ROM_ERR bit in the serial bus control and status register.

Slave Address = 1010 000

Reference(0)

Word Address 00h

Byte 3 (0)

Word Address 01h

Byte 2 (0)

Word Address 02h

Byte 1 (0)

Word Address 03h

Byte 0 (0)

Word Address 04h

RSVD

Reference(1)

Word Address 08h

Reference(n)

Word Address 8

× (n–1)

Byte 3 (n)

Word Address 8

× (n–1) + 1

Byte 2 (n)

Word Address 8

× (n–1) + 2

Byte 1 (n)

Word Address 8

× (n–1) + 3

Byte 0 (n)

Word Address 8

× (n–1) + 4

RSVD

EOL

Word Address 8

× (n)

Figure 14. EEPROM Data Format

The byte at the EEPROM word address 00h must either contain a valid PCI offset, as listed in Table 8, or an

end-of-list (EOL) indicator. The EOL indicator is a byte value of FFh, and indicates the end of the data to load

from the EEPROM. Only doubleword registers are loaded from the EEPROM, and all bit fields must be

considered when programming the EEPROM.

The serial EEPROM is addressed at slave address 1010000b by the PCI1221. All hardware address bits for

the EEPROM should be tied to the appropriate level to achieve this address. The serial EEPROM chip in the

sample application circuit (Figure 8) assumes the 1010b high address nibble. The lower three address bits are

terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND.

When a valid offset reference is read, four bytes are read from the EEPROM, MSB first, as illustrated in

Figure 13. The address autoincrements after every byte transfer according to the doubleword read protocol.

Note that the word addresses align with the data format illustrated in Figure 14. The PCI1221 continues to load

data from the serial EEPROM until an end-of-list indicator is read. Three reserved bytes are stuffed to maintain

eight byte data structures.

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