PCI1221 datasheet(46/123 Pages) TI

46 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Table 16. Command Register

BIT

SIGNAL

TYPE

FUNCTION

15–10

RSVD

Reserved. Bits 15–10 are read only and return 0s when read. Write transactions have no effect.

FBB_EN

Fast back-to-back enable. The PCI1221 does not generate fast back-to-back transactions; therefore, bit

9 is read only and returns 0s when read.

SERR_EN

R/W

System Error (SERR) enable. Bit 8 controls the enable for the SERR driver on the PCI interface. SERR

can be asserted after detecting an address parity error on the PCI bus. Both bit 8 and bit 6 must be set

for the PCI1221 to report address parity errors.

0 = Disable SERR output driver (default)

1 = Enable SERR output driver

STEP_EN

Address/data stepping control. The PCI1221 does not support address/data stepping, and bit 7 is

hardwired to 0. Write transactions to this bit have no effect.

PERR_EN

R/W

Parity error response enable. Bit 6 controls the PCI1221’s response to parity errors through PERR. Data

parity errors are indicated by asserting PERR, whereas address parity errors are indicated by asserting

SERR.

0 = PCI1221 ignores detected parity error (default)

1 = PCI1221 responds to detected parity errors

VGA_EN

VGA palette snoop. Bit 5 controls how PCI devices handle accesses to video graphics array (VGA) palette

registers. The PCI1221 does not support VGA palette snooping; therefore, this bit is hardwired to 0. Bit

5 is read only and returns 0 when read. Write transactions to this bit have no effect.

MWI_EN

Memory write and invalidate enable. Bit 4 controls whether a PCI initiator device can generate memory

write and Invalidate commands. The PCI1221 controller does not support memory write and invalidate

commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. Bit 4 is read only

and returns 0 when read. Write transactions to this bit have no effect.

SPECIAL

Special cycles. Bit 3 controls whether or not a PCI device ignores PCI special cycles. The PCI1221 does

not respond to special cycle operations; therefore, this bit is hardwired to 0. Bit 3 is read only and returns

0 when read. Write transactions to this bit have no effect.

MAST_EN

R/W

Bus master control. Bit 2 controls whether or not the PCI1221 can act as a PCI bus initiator (master). The

PCI1221 can take control of the PCI bus only when this bit is set.

0 = Disables the PCI1221’s ability to generate PCI bus accesses (default)

1 = Enables the PCI1221’s ability to generate PCI bus accesses

MEM_EN

R/W

Memory space enable. Bit 1 controls whether or not the PCI1221 can claim cycles in PCI memory space.

0 = Disables the PCI1221’s response to memory space accesses (default)

1 = Enables the PCI1221’s response to memory space accesses

IO_EN

R/W

I/O space control. Bit 0 controls whether or not the PCI1221 can claim cycles in PCI I/O space.

0 = Disables the PCI1221 from responding to I/O space accesses (default)

1 = Enables the PCI1221 to respond to I/O space accesses

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