PCI1221 datasheet(36/123 Pages) TI

36 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PC Card functional and CSC interrupts (continued)

The naming convention for PC Card signals describes the function for 16-bit memory, I/O cards, and CardBus.

For example, READY(IREQ)//CINT includes READY for 16-bit memory cards, IREQ for 16-bit I/O cards, and

CINT for CardBus cards. The 16-bit memory card signal name is first, with the I/O card signal name second,

enclosed in parentheses. The CardBus signal name follows after a forward double slash (//).

The PC Card standard describes the power-up sequence that must be followed by the PCI1221 when an

insertion event occurs and the host requests that the socket VCC and VPP be powered. Upon completion of this

power-up sequence, the PCI1221 interrupt scheme can be used to notify the host system (see Table 11),

denoted by the power cycle complete event. This interrupt source is considered a PCI1221 internal event

because it depends on the completion of applying power to the socket rather than on a signal change at the PC

Card interface.

interrupt masks and flags

Host software may individually mask (or disable) most of the potential interrupt sources listed in Table 11 by

setting the appropriate bits in the PCI1221. By individually masking the interrupt sources listed, software can

control those events that cause a PCI1221 interrupt. Host software has some control over the system interrupt

the PCI1221 asserts by programming the appropriate routing registers. The PCI1221 allows host software to

route PC Card CSC and PC Card functional interrupts to separate system interrupts. Interrupt routing somewhat

specific to the interrupt signaling method used is discussed in more detail in the following sections.

When an interrupt is signaled by the PCI1221, the interrupt service routine must determine which of the events

listed in Table 10 caused the interrupt. Internal registers in the PCI1221 provide flags that report the source of

an interrupt. By reading these status bits, the interrupt service routine can determine the action to be taken.

Table 10 details the registers and bits associated with masking and reporting potential interrupts. All interrupts

can be masked except the functional PC Card interrupts, and an interrupt status flag is available for all types

of interrupts.

Notice that there is not a mask bit to stop the PCI1221 from passing PC Card functional interrupts through to

the appropriate interrupt scheme. These interrupts are not valid until the card is properly powered, and there

should never be a card interrupt that does not require service after proper initialization.

Various methods of clearing the interrupt flag bits are listed in Table 10. The flag bits in the ExCA registers (16-bit

PC Card-related interrupt flags) can be cleared using two different methods. One method is an explicit write of

1 to the flag bit to clear, and the other is by reading the flag bit register. The selection of flag bit clearing is made

by bit 2 in the global control register (ExCA offset 1Eh/5Eh/81Eh), and defaults to the

flag cleared on

read method.

The CardBus-related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event

software should not program the chip through both register sets when a CardBus card is functioning.

using parallel IRQ interrupts

The seven multifunction terminals, MFUNC6:0, implemented in the PCI1221 may be routed to obtain a subset

of the ISA IRQs . The IRQ choices provide ultimate flexibility in PC Card host interruptions. To use the parallel

ISA type IRQ interrupt signaling, software must program the device control register, located at PCI offset 92h,

to select the parallel IRQ signaling scheme. Refer to the

multifunction routing register description on page 62

for details on configuring the multifunction terminals.

A system using parallel IRQs requires (at a minimum) one PCI terminal, INTA, to signal CSC events. This

requirement is dictated by certain card and socket services software. The INTA requirement calls for routing

the MFUNC0 terminal for INTA signaling. The INTRTIE bit is used, in this case, to route socket 1 interrupt events

to INTA. This leaves (at a maximum) six different IRQs to support legacy 16-bit PC Card functions.

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