PCI1221 datasheet(27/123 Pages) TI

27 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

zoom video support (continued)

Figure 5 illustrates an implementation using standard three-state bus drivers with active-low output enables.

ZVSEL0 is an active-low output indicating that the Socket 0 ZV mode is enabled, and ZVSEL1 is an active-low

output indicating that Socket 1 ZV is enabled. When both sockets have ZV mode enabled, the PCI1221 defaults

to indicating socket 0 enabled through ZVSEL0; however, the PORTSEL bit in the card control register allows

software to select the socket ZV source priority. Table 6 illustrates the functionality of the ZV output signals.

Table 6. PC Card Card-Detect and Voltage-Sense Connections

INPUTS

OUTPUTS

PORTSEL

SOCKET 0 ENABLE

SOCKET 1 ENABLE

ZVSEL0

ZVSEL1

ZVSTAT

Also shown in Figure 5 is a third ZV source that may be provided from a source such as a high-speed serial bus

like IEEE1394. The ZVSTAT signal provides a mechanism to switch the third ZV source. ZVSTAT is an

active-high output indicating that one of the PCI1221 sockets is enabled for ZV mode. The implementation

shown in Figure 5 can be used if PC Card ZV is prioritized over other sources.

SPKROUT and CAUDPWM usage

SPKROUT carries the digital audio signal from the PC Card to the system. When a 16-bit PC Card is configured

for I/O mode, the BVD2 pin becomes SPKR. This terminal is also used in CardBus binary audio applications,

and is referred to as CAUDIO. SPKR passes a TTL level digital audio signal to the PCI1221. The CardBus

CAUDIO signal also can pass a single-amplitude binary waveform. The binary audio signals from the two PC

Card Sockets are XOR’ed in the PCI1221 to produce SPKROUT. This output is enabled by the SPKROUTEN

bit in the card control register.

Older controllers support CAUDIO in binary or PWM mode but use the same pin (SPKROUT). Some audio chips

may not support both modes on one pin and may have a separate pin for binary and PWM. The PCI1221

implementation includes a signal for PWM, CAUDPWM, which can be routed to a MFUNC terminal. The

AUD2MUX bit located in the card control register is programmed on a per socket function basis to route a

CardBus CAUDIO PWM terminal to CAUDPWM. If both CardBus functions enable CAUDIO PWM routing to

CAUDPWM, then socket 0 audio takes precedence. Refer to the

multifunction routing register description on

page 62 for details on configuring the MFUNC terminals.

Figure 6 provides an illustration of a sample application using SPKROUT and CAUDPWM.

Speaker

Subsystem

BINARY_SPKR

System

Core Logic

PCI1221

CAUDPWM

SPKROUT

PWM_SPKR

Figure 6. Sample Application of SPKROUT and CAUDPWM

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