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power-management capabilities register

Bit

Name

Power-management capabilities

Type

Default

Power-management capabilities

Type:

Read only (see individual bit descriptions)

Offset:

A2h (functions 0, 1)

Default:

7E21h

Description: The power-management capabilities register contains information on the capabilities of the

PC Card function related to power management. Both PCI1221 CardBus bridge functions

support D0, D2, and D3 power states. See Table 27 for a complete description of the register

contents.

Table 27. Power-Management Capabilities Register

BIT

SIGNAL

TYPE

FUNCTION

15–11

PME_CAP

PME support. This 5-bit field indicates the power states from which the PCI1221 supports asserting PME.

A 0 for any bit indicates that the CardBus function cannot assert PME from that power state. These five

bits return 01111b when read. Each of these bits is described below:

Bit 15 contains the value 0, indicating that PME cannot be asserted from D3cold state.

Bit 14 contains the value 1, indicating that PME can be asserted from D3hot state.

Bit 13 contains the value 1, indicating that PME can be asserted from D2 state.

Bit 12 contains the value 1, indicating that PME can be asserted from D1 state.

Bit 11 contains the value 1, indicating that PME can be asserted from the D0 state.

D2_CAP

D2 support. Bit 10 returns a 1 when read, indicating that the CardBus function supports the D2 device

power state.

D1_CAP

D1 support. Bit 9 returns a 1 when read, indicating that the CardBus function supports the D1 device

power state.

DYN_DATA

Dynamic data support. Bit 8 returns a 0 when read, indicating that the CardBus function does not report

dynamic power consumption data.

7–6

RSVD

Reserved. These bits are reserved and return 00b when read.

DSI

Device-specific initialization. Bit 5 is read only and returns 1 when read, indicating that the CardBus

controller functions require special initialization (beyond the standard PCI configuration header) before the

generic class device driver is able to use it.

AUX_PWR

Auxiliary power source. Bit 4 is meaningful only if bit 15 (D3cold supporting PME) is set. When set, bit 4

indicates that the function supplies its own auxiliary power source.

PMECLK

PME clock. Bit 3 is read only and returns 0 when read, indicating that no host bus clock is required for the

PCI1221 to generate PME.

2–0

VERSION

Version. Bits 2–0 return 001b when read, indicating that there are four bytes of general-purpose power

management (PM) registers as described in the

PCI Bus Power Management Interface Specification,

Revision 1.0.

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