PCI1221 datasheet(12/123 Pages) TI

12 / 123 page

PCI1221 GHK/PDV

PC CARD CONTROLLERS

SCPS042 – JULY 1998

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions

The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The

terminal numbers are also listed for convenient reference.

power supply

TERMINAL

FUNCTION

NAME

PDV NUMBER

GHK NUMBER

FUNCTION

GND

13, 22, 44, 75, 96, 129, 153,

167, 181, 194, 207

G2, J5, P2, P9, V14, K18, E18,

F12, B10, E8, C5

Device ground terminals

VCC

7, 31, 64, 86, 113, 143, 164,

175, 187, 201

F3, L3, U7, W12, N15, G19,

B14, A11, C9, E7

Power supply terminal for core logic (3.3 V)

VCCA

120

M17

Clamp voltage for PC Card A interface. Indicates Card A

signaling environment, 5 V or 3.3 V.

VCCB

Clamp voltage for PC Card B interface. Indicates Card B

signaling environment, 5 V or 3.3 V.

VCCI

148

F18

Clamp voltage for interrupt subsystem interface and

miscellaneous I/O. (5 V or 3.3 V)

VCCP

1, 178

D1, E11

Clamp voltage for PCI signaling (5 V or 3.3 V)

PC Card power switch

TERMINAL

I/O

NAME

PIN NUMBER

I/O

TYPE

FUNCTION

NAME

PDV

GHK

TYPE

CLOCK

151

E19

I/O

Three-line power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK.

CLOCK defaults to an input, but can be changed to a PCI1221 output by using the P2CCLK bit in the

System Control Register. The TPS2206 defines the maximum frequency of this signal to be 2 MHz.

If a system design defines this terminal as an output, then this terminal requires an external pull down

resister. The frequency of the PCI1221 output CLOCK is derived from dividing the PCI CLK by 36.

DATA

152

F14

Three-line power switch data. DATA is used to serially communicate socket power control information

to the power switch.

LATCH

150

F17

Three-line power switch latch. LATCH is asserted by the PCI1221 to indicate to the PC Card power

switch that the data on the DATA line is valid. When a pulldown resistor is implemented on this

terminal, the MFUNC4 and MFUNC1 terminals provide the serial EEPROM SCL and SDA interface.

PCI system

TERMINAL

NAME

PIN NUMBER

I/O

TYPE

FUNCTION

NAME

PDV

GHK

TYPE

PCLK

180

A10

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at

the rising edge of PCLK.

PRST

166

A14

PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1221 to place all output buffers

in a high-impedance state and reset all internal registers. When PRST is asserted, the device is

completely nonfunctional. After PRST is deasserted, the PCI1221 is in its default state.

When the SUSPEND and PRST are asserted, the device is protected from the PRST clearing the internal

registers. All outputs are placed in a high-impedance state, but the contents of the registers are

preserved.

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